參數(shù)資料
型號: ADUC7023BCPZ62I-R7
廠商: Analog Devices Inc
文件頁數(shù): 31/96頁
文件大?。?/td> 0K
描述: IC MCU 12BIT 62KB FLASH 32LFCSP
標(biāo)準(zhǔn)包裝: 1,500
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 44MHz
連通性: I²C,SPI
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 12
程序存儲器容量: 64KB(32K x 16)
程序存儲器類型: 閃存
RAM 容量: 2K x 32
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b,D/A 4x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 32-WFQFN 裸露焊盤,CSP
包裝: 帶卷 (TR)
Data Sheet
ADuC7023
| Page 37 of 96
NONVOLATILE FLASH/EE MEMORY
The ADuC7023 incorporates Flash/EE memory technology on
chip to provide the user with nonvolatile, in-circuit reprogram-
mable memory space.
Like EEPROM, flash memory can be programmed in-system at
a byte level, although it must first be erased. The erase is performed
in page blocks. As a result, flash memory is often and more
correctly referred to as Flash/EE memory.
The Flash/EE memory represents a step closer to the ideal memory
device that includes nonvolatility, in-circuit programmability,
high density, and low cost. Incorporated in the ADuC7023,
Flash/EE memory technology allows the user to update program
code space in-circuit, without needing to replace one-time
programmable (OTP) devices at remote operating nodes.
Each part contains a 64 kB array of Flash/EE memory. The lower
62 kB are available to the user, and the upper 2 kB contain
permanently embedded firmware, allowing in-circuit serial
download. These 2 kB of embedded firmware also contain a
power-on configuration routine that downloads factory-
calibrated coefficients to the various calibrated peripherals
(such as ADC, temperature sensor, and band gap references).
This 2 kB embedded firmware is hidden from user code.
Flash/EE Memory Reliability
The Flash/EE memory arrays on the parts are fully qualified for
two key Flash/EE memory characteristics: Flash/EE memory
cycling endurance and Flash/EE memory data retention.
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. A single
endurance cycle is composed of four independent, sequential
events, defined as:
1. Initial page erase sequence.
2. Read/verify sequence (single Flash/EE).
3. Byte program sequence memory.
4. Second read/verify sequence (endurance cycle).
In reliability qualification, every half word (16-bit wide)
location of the three pages (top, middle, and bottom) in the
Flash/EE memory is cycled 10,000 times from 0x0000 to
0xFFFF. As indicated in Table 1, the Flash/EE memory
endurance qualification is carried out in accordance with
JEDEC Retention Lifetime Specification A117 over the
industrial temperature range of 40° to +125°C. The results
allow the specification of a minimum endurance figure over a
supply temperature of 10,000 cycles.
Retention quantifies the ability of the Flash/EE memory to
retain its programmed data over time. Again, the parts are
qualified in accordance with the formal JEDEC Retention
Lifetime Specification (A117) at a specific junction temperature
(TJ = 85°C). As part of this qualification procedure, the
Flash/EE memory is cycled to its specified endurance limit
before data retention is characterized. This means that the
Flash/EE memory is guaranteed to retain its data for its fully
specified retention lifetime every time the Flash/EE memory is
reprogrammed. In addition, note that retention lifetime, based
on activation energy of 0.6 eV, derates with TJ as shown in
150
300
450
600
30
40
55
70
85
100
125
135
150
RE
T
E
NT
IO
N
(
Y
ears)
0
08675-
024
JUNCTION TEMPERATURE (°C)
Figure 30. Flash/EE Memory Data Retention
PROGRAMMING
The 62 kB of Flash/EE memory can be programmed in circuit,
using the serial download mode or the provided JTAG mode.
Downloading (In-Circuit Programming) via I2C
The ADuC7023 facilitates code download via the the I2C port.
The parts enter download mode after a reset or power cycle if
the BM pin is pulled low through an external 1 k resistor and
Flash Addess 0x80014 = 0xFFFFFFFF. Once in download mode,
the user can download code to the full 62 kB of Flash/EE
memory while the device is in-circuit in its target application
hardware. An executable PC I2C download is provided as part
of the development system for serial downloading via the I2C. A
USB to I2C download dongle can be purchased from Analog
Devices, Inc. This board connects to the USB port of a PC and
to the I2C port of the ADuC7023. The part number is USB-
I2C/LIN-CONV-Z.
The AN-806 Application Note describes the protocol for serial
downloading via the I2C in more detail.
JTAG Access
The JTAG protocol uses the on-chip JTAG interface to facilitate
code download and debug.
To access the part via the JTAG interface, the P0.0/BM pin must
be set high to enable P0.1/P0.2/P0.3 as JTAG pins.
When debugging, user code should not write to the P0.1/P0.2
and P0.3 pins. If user code toggles any of these pins, JTAG
debug pods are not able to connect to the ADuC7023. In case
this happens, the user should have a function in code that can
be called externally to mass erase the part. Alternatively, the
user should ensure that Flash Address 0x80014 is erased to
allow erasing of the part through the I2C interface.
Rev. E
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