參數(shù)資料
型號： ADUC7020
廠商： Analog Devices, Inc.
英文描述： Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
中文描述： 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器
文件頁數(shù)： 38/80頁
文件大小： 840K
代理商： ADUC7020
ADuC702x Series
Preliminary Technical Data
Rev. PrB | Page 38 of 80
Using the DACs
The on-chip DAC architecture consists of a resistor string DAC
followed by an output buffer amplifier, the functional
equivalent of which is illustrated in Figure 17.
OUTPUT
BUFFER
BYPASSED
FROM MCU
DAC0
R
R
R
R
R
AVDD
VREF
DACREF
Figure 17: DAC structure
As illustrated in Figure 17, the reference source for each DAC is
user selectable in software. It can be either AVDD, VREF or
DACREF. In 0-to-AVDD mode, the DAC output transfer
function spans from 0 V to the voltage at the AVDD pin. In 0-
to-DACREF mode, the DAC output transfer function spans
from 0 V to the voltage at the DACREF pin. In 0-to-VREF
mode, the DAC output transfer function spans from 0 V to the
internal 2.5V reference, VREF. The DAC output buffer amplifier
features a true rail-to-rail output stage implementation. This
means that, unloaded, each output is capable of swinging to
within less than 5 mV of both AVDD and ground. Moreover,
the DAC’s linearity specification (when driving a 5k resistive
load to ground) is guaranteed through the full transfer function
except codes 0 to 100, and, in 0-to-AVDD mode only, codes
3995 to 4095. Linearity degradation near ground and VDD is
caused by saturation of the output amplifier, and a general
representation of its effects (neglecting offset and gain error) is
illustrated in Figure 18. The dotted line in Figure 18 indicates
the ideal transfer function, and the solid line represents what
the transfer function might look like with endpoint
nonlinearities due to saturation of the output amplifier. Note
that Figure 18 represents a transfer function in 0-to-AV
DD
mode
only. In 0-to-V
REF
or 0-to-DAC
REF
modes (with V
REF
< AV
DD
or
DAC
REF
< AV
DD
) the lower nonlinearity would be similar, but
the upper portion of the transfer function would follow the
“ideal” line right to the end (V
REF
in this case, not AV
DD
),
showing no signs of endpoint linearity errors.
AV
DD
AV
DD
-100mV
100mV
000h
FFFh
~
~
~
Figure 18: endpoint nonlinearities due to amplifier saturation
The endpoint nonlinearities conceptually illustrated in Figure
18 get worse as a function of output loading. Most of the
ADuC702x’s datasheet specifications assume a 5 k
resistive
load to ground at the DAC output. As the output is forced to
source or sink more current, the nonlinear regions at
the top or bottom (respectively) of Figure 18 become larger.
With larger current demands, this can significantly limit output
voltage swing.
To reduce the effects of the saturation of the output amplifier at
values close to ground and to give reduced offset and gain
errors, the internal buffer can be bypassed in the DAC control
register. This allows a full rail-to-rail output from the DAC
which should then be buffered externally using a dual supply
op-amp in order to get a rail-to-rail output. This external buffer
should be located as near as physically possible to the DAC
output pin on the PCB.
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