參數(shù)資料
型號： ADSP-TS203SABP-050
廠商： Analog Devices Inc
文件頁數(shù)： 13/48頁
文件大?。?/td> 0K
描述： IC DSP FLOAT/FIXED 500MHZ 576BGA
標準包裝： 1
系列： TigerSHARC®
類型： 定點/浮點
接口： 主機接口，連接端口，多處理器
時鐘速率： 500MHz
非易失內(nèi)存： 外部
芯片上RAM： 512kB
電壓 - 輸入/輸出： 2.50V
電壓 - 核心： 1.05V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 576-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 576-BGA-ED（25x25）
包裝： 托盤
其它名稱： ADSP-TS203SABP050
ADSP-TS203SABP050-ND
Rev. D
|
Page 20 of 48
|
May 2012
SPECIFICATIONS
Note that component specifications are subject to change with
out notice. For information on link port electrical characteris-
OPERATING CONDITIONS
Parameter
Description
Test Conditions
Grade1
1 Specifications vary for different grades (for example, SABP–060, SABP–050, SWBP–050). For more information on part grades, see Ordering Guide on Page 47.
Min
Typ
Max
Unit
VDD
Internal Supply Voltage
@ CCLK = 500 MHz
050
1.00
1.05
1.10
V
VDD_A
Analog Supply Voltage
@ CCLK = 500 MHz
050
1.00
1.05
1.10
V
VDD_IO
I/O Supply Voltage
(all)
2.38
2.50
2.63
V
VDD_DRAM
Internal DRAM Supply Voltage
@ CCLK = 500 MHz
050
1.425
1.500
1.575
V
TCASE
Case Operating Temperature
A
–40
+85
°C
TCASE
Case Operating Temperature
B
0
+85
°C
VIH1
High Level Input Voltage2, 3
2 VIH1 specification applies to input and bidirectional pins: SCLKRAT2–0, SCLK, ADDR31–0, DATA63–0, RD, WRL, ACK, BRST, BR7–0, BOFF, HBR, HBG, MSSD3–0, RAS,
CAS, SDCKE, SDWE, TCK, FLAG3–0, DS2–0, ENEDREG.
3 Values represent dc case. During transitions, the inputs may overshoot or undershoot to the voltage shown in Table 18, based on the transient duty cycle. The dc case is
equivalent to 100% duty cycle.
@ VDD, VDD_IO = Max
(all)
1.7
3.63
V
VIH2
High Level Input Voltage3, 4
4 VIH2 specification applies to input and bidirectional pins: TDI, TMS, TRST, CIMP1–0, ID2–0, LxBCMPI, LxACKI, POR_IN, RST_IN, IRQ3–0, CPA, DPA, DMAR3–0.
@ VDD, VDD_IO = Max
(all)
1.9
3.63
V
VIL
Low Level Input Voltage3, 5
5 Applies to input and bidirectional pins.
@ VDD, VDD_IO = Min
(all)
–0.33
+0.8
V
IDD
VDD Supply Current, Typical Activity
6
6 For details on internal and external power calculation issues, including other operating conditions, see EE-170, Estimating Power for the ADSP-TS203S.
@ CCLK = 500 MHz, VDD = 1.05 V,
TCASE = 25°C
050
2.06
A
IDD_A
VDD_A Supply Current, Typical Activity
@ CCLK = 500 MHz, VDD = 1.05 V,
TCASE = 25°C
050
20
50
mA
IDD_IO
VDD_IO Supply Current, Typical Activity
6
@ SCLK = 62.5 MHz, VDD_IO = 2.5 V,
TCASE = 25°C
(all)
0.15
A
IDD_DRAM
VDD_DRAM Supply Current,
Typical Activity6
@ CCLK = 500 MHz, VDD_DRAM = 1.5 V,
TCASE = 25°C
050
0.25
0.40
A
VREF
Voltage Reference
(all)
(VDD_IO ×0.56)±5%
V
SCLK_VREF
Voltage Reference
(all)
(VCLOCK_DRIVE × 0.56) ±5%
V
Table 18. Maximum Duty Cycle for Input Transient Voltage
VIN Max (V)
1
1 The individual values cannot be combined for analysis of a single instance of overshoot or undershoot. The worst case observed value must fall within one of the voltages
specified and the total duration of the overshoot or undershoot (exceeding the 100% case) must be less than or equal to the corresponding
duty cycle.
VIN Min (V)
1
Maximum Duty Cycle2
2 Duty cycle refers to the percentage of time the signal exceeds the value for the 100% case. This is equivalent to the measured duration of a single instance of overshoot or
undershoot as a percentage of the period of occurrence. The practical worst case for period of occurrence for either overshoot or undershoot is 2 × tSCLK.
+3.63
–0.33
100%
+3.64
–0.34
90%
+3.70
–0.40
50%
+3.78
–0.48
30%
+3.86
–0.56
17%
+3.93
–0.63
10%
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