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| 型號： | ADSP-TS202SABPZ050 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 44/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR 500MHZ 576BGA |
| 標準包裝： | 1 |
| 系列： | TigerSHARC® |
| 類型： | 定點/浮點 |
| 接口： | 主機接口，連接端口，多處理器 |
| 時鐘速率： | 500MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 1.5MB |
| 電壓 - 輸入/輸出： | 2.50V |
| 電壓 - 核心： | 1.05V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 576-BBGA 裸露焊盤 |
| 供應商設(shè)備封裝： | 576-BGA-ED（25x25） |
| 包裝： | 托盤 |
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ADSP-TS202S
Rev. C
|
Page 5 of 48
|
December 2006
up a total of eight circular buffers. The IALUs handle address
pointer wraparound automatically, reducing overhead, increas-
ing performance, and simplifying implementation. Circular
buffers can start and end at any memory location.
Because the IALU’s computational pipeline is one cycle deep, in
most cases integer results are available in the next cycle. Hard-
ware (register dependency check) causes a stall if a result is
unavailable in a given cycle.
PROGRAM SEQUENCER
The ADSP-TS202S processor’s program sequencer supports the
following:
A fully interruptible programming model with flexible pro-
gramming in assembly and C/C++ languages; handles
hardware interrupts with high throughput and no aborted
instruction cycles
A 10-cycle instruction pipeline—four-cycle fetch pipe and
six-cycle execution pipe—computation results available
two cycles after operands are available
Supply of instruction fetch memory addresses; the
sequencer’s instruction alignment buffer (IAB) caches up
to five fetched instruction lines waiting to execute; the pro-
gram sequencer extracts an instruction line from the IAB
and distributes it to the appropriate core component for
execution
Management of program structures and program flow
determined according to JUMP, CALL, RTI, RTS instruc-
tions, loop structures, conditions, interrupts, and software
exceptions
Branch prediction and a 128-entry branch target buffer
(BTB) to reduce branch delays for efficient execution of
conditional and unconditional branch instructions and
zero-overhead looping; correctly predicted branches that
are taken occur with zero overhead cycles, overcoming the
five-to-nine stage branch penalty
Compact code without the requirement to align code in
memory; the IAB handles alignment
Interrupt Controller
The DSP supports nested and nonnested interrupts. Each inter-
rupt type has a register in the interrupt vector table. Also, each
has a bit in both the interrupt latch register and the interrupt
mask register. All interrupts are fixed as either level-sensitive or
edge-sensitive, except the IRQ3–0 hardware interrupts, which
are programmable.
The DSP distinguishes between hardware interrupts and soft-
ware exceptions, handling them differently. When a software
exception occurs, the DSP aborts all other instructions in the
instruction pipe. When a hardware interrupt occurs, the DSP
continues to execute instructions already in the instruction pipe.
Flexible Instruction Set
The 128-bit instruction line, which can contain up to four 32-bit
instructions, accommodates a variety of parallel operations for
concise programming. For example, one instruction line can
direct the DSP to conditionally execute a multiply, an add, and a
subtract in both computation blocks while it also branches to
another location in the program. Some key features of the
instruction set include
Algebraic assembly language syntax
Direct support for all DSP, imaging, and video arithmetic
types
Eliminates toggling DSP hardware modes because modes
are supported as options (for example, rounding, satura-
tion, and others) within instructions
Branch prediction encoded in instruction; enables zero-
overhead loops
Parallelism encoded in instruction line
Conditional execution optional for all instructions
User-defined partitioning between program and data
memory
DSP MEMORY
The DSP’s internal and external memory is organized into a
unified memory map, which defines the location (address) of all
elements in the system, as shown in Figure 3.
The memory map is divided into four memory areas—host
space, external memory, multiprocessor space, and internal
memory—and each memory space, except host memory, is sub-
divided into smaller memory spaces.
The ADSP-TS202S processor internal memory has 12M bits of
on-chip DRAM memory, divided into six blocks of 2M bits
(64K words × 32 bits). Each block—M0, M2, M4, M6, M8, and
M10—can store program instructions, data, or both, so applica-
tions can configure memory to suit specific needs. Placing
program instructions and data in different memory blocks,
however, enables the DSP to access data while performing an
instruction fetch. Each memory segment contains a 128K bit
cache to enable single-cycle accesses to internal DRAM.
The six internal memory blocks connect to the four 128-bit wide
internal buses through a crossbar connection, enabling the DSP
to perform four memory transfers in the same cycle. The DSP’s
internal bus architecture provides a total memory bandwidth of
28G bytes per second, enabling the core and I/O to access eight
32-bit data-words and four 32-bit instructions each cycle. The
DSP’s flexible memory structure enables
DSP core and I/O accesses to different memory blocks in
the same cycle
DSP core access to three memory blocks in parallel—one
instruction and two data accesses
Programmable partitioning of program and data memory
Program access of all memory as 32-, 64-, or 128-bit
words—16-bit words with the DAB
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參數(shù)描述 |
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| ADSP-TS203SABP-050 | 功能描述:IC DSP FLOAT/FIXED 500MHZ 576BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:TigerSHARC® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-TS203SABP-05X | 制造商:Analog Devices 功能描述: |
| ADSP-TS203SABPZ050 | 功能描述:IC PROCESSOR 500MHZ 576BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:TigerSHARC® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-TS203SBBPZ050 | 制造商:Analog Devices 功能描述:DSP - Bulk |
| ADSQ-1410 | 制造商:MURATA-PS 制造商全稱:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter |
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