參數(shù)資料
型號(hào)： ADSP-TS202SABPZ050
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 23/48頁(yè)
文件大?。?/td> 0K
描述： IC PROCESSOR 500MHZ 576BGA
標(biāo)準(zhǔn)包裝： 1
系列： TigerSHARC®
類(lèi)型： 定點(diǎn)/浮點(diǎn)
接口： 主機(jī)接口，連接端口，多處理器
時(shí)鐘速率： 500MHz
非易失內(nèi)存： 外部
芯片上RAM： 1.5MB
電壓 - 輸入/輸出： 2.50V
電壓 - 核心： 1.05V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 576-BBGA 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 576-BGA-ED（25x25）
包裝： 托盤(pán)
ADSP-TS202S
Rev. C
|
Page 3 of 48
|
December 2006
GENERAL DESCRIPTION
The ADSP-TS202S TigerSHARC processor is an ultrahigh per-
formance, static superscalar processor optimized for large signal
processing tasks and communications infrastructure. The DSP
combines very wide memory widths with dual computation
blocks—supporting floating-point (IEEE 32-bit and extended
precision 40-bit) and fixed-point (8-, 16-, 32-, and 64-bit) pro-
cessing—to set a new standard of performance for digital signal
processors. The TigerSHARC static superscalar architecture lets
the DSP execute up to four instructions each cycle, performing
24 fixed-point (16-bit) operations or six floating-point
operations.
Four independent 128-bit wide internal data buses, each con-
necting to the six 2M bit memory banks, enable quad-word
data, instruction, and I/O accesses and provide 28G bytes per
second of internal memory bandwidth. Operating at 500 MHz,
the ADSP-TS202S processor’s core has a 2.0 ns instruction cycle
time. Using its single-instruction, multiple-data (SIMD) fea-
tures, the ADSP-TS202S processor can perform four billion
40-bit MACS or one billion 80-bit MACS per second. Table 1
shows the DSP’s performance benchmarks.
The ADSP-TS202S processor is code-compatible with the other
TigerSHARC processors.
The Functional Block Diagram on Page 1 shows the ADSP-
TS202S processor’s architectural blocks. These blocks include
Dual compute blocks, each consisting of an ALU, multi-
plier, 64-bit shifter, and 32-word register file and associated
data alignment buffers (DABs)
Dual integer ALUs (IALUs), each with its own 31-word
register file for data addressing and a status register
A program sequencer with instruction alignment buffer
(IAB) and branch target buffer (BTB)
An interrupt controller that supports hardware and soft-
ware interrupts, supports level- or edge-triggers, and
supports prioritized, nested interrupts
Four 128-bit internal data buses, each connecting to the six
2M-bit memory banks
On-chip DRAM (12M-bit)
An external port that provides the interface to host proces-
sors, multiprocessing space (DSPs), off-chip memory-
mapped peripherals, and external SRAM and SDRAM
A 14-channel DMA controller
Four full-duplex LVDS link ports
Two 64-bit interval timers and timer expired pin
An 1149.1 IEEE compliant JTAG test access port for on-
chip emulation
Figure 2 shows a typical single-processor system with external
SRAM and SDRAM. Figure 4 on Page 8 shows a typical multi-
processor system.
Table 1. General-Purpose Algorithm Benchmarks
at 500 MHz
Benchmark
Speed
Clock
Cycles
32-bit algorithm, 1 billion MACS/s peak performance
1K point complex FFT
1 (Radix 2)
1 Cache preloaded.
18.8 μs
9419
64K point complex FFT
1 (Radix 2)
2.8 ms
1397544
FIR filter (per real tap)
1 ns
0.5
[8 × 8][8 × 8] matrix multiply (complex,
floating-point)
2.8 μs
1399
16-bit algorithm, 4 billion MACS/s peak performance
256 point complex FFT1 (Radix 2)
1.9 μs
928
I/O DMA transfer rate
External port
1G bytes/s
n/a
Link ports (each)
1G bytes/s
n/a
Figure 2. ADSP-TS202S Single-Processor System with External SDRAM
BOFF
CONTROLIMP1–0
DMAR3–0
HBG
HBR
DMA DEVICE
(OPTIONAL)
DATA
MSH
FLAG3–0
ID2–0
IOEN
RAS
CAS
LDQM
HDQM
SDWE
SDCKE
SDA10
IRQ3–0
SCLK
SCLKRAT2–0
SCLK_VREF
VREF
TMR0E
BM
MSSD3–0
BUSLOCK
SDRAM
MEMORY
(OPTIONAL)
CS
RAS
CAS
DQM
WE
CKE
A10
ADDR
DATA
CLK
POR_IN
JTAG
ADSP-TS202S
BMS
CLOCK
LINK
DEVICES
(4 MAX)
(OPTIONAL)
BOOT
EPROM
(OPTIONAL)
ADDR
MEMORY
(OPTIONAL)
OE
DATA
ADDR
DATA
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
ACK
BR7–0
CPA
MS1–0
DATA63–0
DATA
ADDR
CS
ACK
WE
ADDR31–0
D
A
T
A
C
O
N
T
R
O
L
A
D
R
E
S
BRST
REFERENCE
RD
WRH/WRL
DPA
DS2–0
CS
LxCLKINP/N
LxACKO
LxDATI3–0P/N
LxBCMPI
LxBCMPO
LxDATO3–0P/N
LxCLKOUTP/N
LxACKI
IORD
IOWR
RST_OUT
RST_IN
REFERENCE
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ADSP-TS203SABP-050 功能描述:IC DSP FLOAT/FIXED 500MHZ 576BGA RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:TigerSHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類(lèi)型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類(lèi)型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤(pán)
ADSP-TS203SABP-05X 制造商:Analog Devices 功能描述:
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ADSP-TS203SBBPZ050 制造商:Analog Devices 功能描述:DSP - Bulk
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