- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1900 > ADSP-BF592BCPZ (Analog Devices Inc)IC DSP CTRLR 64LFCSP PDF資料下載
參數(shù)資料
| 型號： | ADSP-BF592BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 44/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CTRLR 64LFCSP |
| 視頻文件： | Blackfin? BF592 Introduction |
| 特色產(chǎn)品： | Blackfin Embedded Processor |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Blackfin® |
| 類型： | 定點(diǎn) |
| 接口： | I²C，I²S，IrDA，PPI，SPI，SPORT，UART |
| 時鐘速率： | 400MHz |
| 非易失內(nèi)存： | ROM（64 kB） |
| 芯片上RAM： | 64kB |
| 電壓 - 輸入/輸出： | 1.8V，2.5V，3.3V |
| 電壓 - 核心： | 1.29V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁當(dāng)前第44頁
Rev. B
|
Page 9 of 44
|
July 2013
Note that when a GPIO pin is used to trigger wake from deep
sleep, the programmed wake level must linger for at least 10ns
to guarantee detection.
Hibernate State—Maximum Static Power Savings
The hibernate state maximizes static power savings by disabling
clocks to the processor core (CCLK) and to all of the peripherals
(SCLK), as well as signaling an external voltage regulator that
VDDINT can be shut off. Any critical information stored inter-
nally (for example, memory contents, register contents, and
other information) must be written to a nonvolatile storage
device prior to removing power if the processor state is to be
preserved. Writing b#0 to the HIBERNATE bit causes
EXT_WAKE to transition low, which can be used to signal an
external voltage regulator to shut down.
Since VDDEXT can still be supplied in this mode, all of the exter-
nal pins three-state, unless otherwise specified. This allows
other devices that may be connected to the processor to still
have power applied without drawing unwanted current.
As long as VDDEXT is applied, the VR_CTL register maintains its
state during hibernation. All other internal registers and memo-
ries, however, lose their content in the hibernate state.
Power Savings
As shown in Table 3, the processor supports two different
power domains, which maximizes flexibility while maintaining
compliance with industry standards and conventions. By isolat-
ing the internal logic of the processor into its own power
domain, separate from other I/O, the processor can take advan-
tage of dynamic power management without affecting the other
various power domains, but all domains must be powered
according to the appropriate Specifications table for processor
operating conditions, even if the feature/peripheral is not used.
The dynamic power management feature of the processor
allows both the processor’s input voltage (VDDINT) and clock fre-
quency (fCCLK) to be dynamically controlled.
The power dissipated by a processor is largely a function of its
clock frequency and the square of the operating voltage. For
example, reducing the clock frequency by 25% results in a 25%
reduction in dynamic power dissipation, while reducing the
voltage by 25% reduces dynamic power dissipation by more
than 40%. Further, these power savings are additive, in that if
the clock frequency and supply voltage are both reduced, the
power savings can be dramatic, as shown in the following
equations.
where:
fCCLKNOM is the nominal core clock frequency
fCCLKRED is the reduced core clock frequency
VDDINTNOM is the nominal internal supply voltage
VDDINTRED is the reduced internal supply voltage
TNOM is the duration running at fCCLKNOM
TRED is the duration running at fCCLKRED
VOLTAGE REGULATION
The ADSP-BF592 processor requires an external voltage regula-
tor to power the VDDINT domain. To reduce standby power
consumption, the external voltage regulator can be signaled
through EXT_WAKE to remove power from the processor core.
This signal is high-true for power-up and may be connected
directly to the low-true shut-down input of many common
regulators.
While in the hibernate state, the external supply, VDDEXT, can
still be applied, eliminating the need for external buffers. The
external voltage regulator can be activated from this power-
down state by asserting the RESET pin, which then initiates a
boot sequence. EXT_WAKE indicates a wakeup to the external
voltage regulator.
The power good (PG) input signal allows the processor to start
only after the internal voltage has reached a chosen level. In this
way, the startup time of the external regulator is detected after
hibernation. For a complete description of the power-good
functionality, refer to the ADSP-BF59x Blackfin Processor Hard-
ware Reference.
CLOCK SIGNALS
The processor can be clocked by an external crystal, a sine wave
input, or a buffered, shaped clock derived from an external
clock oscillator.
If an external clock is used, it should be a TTL-compatible signal
and must not be halted, changed, or operated below the speci-
fied frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.
Alternatively, because the processor includes an on-chip oscilla-
tor circuit, an external crystal may be used. For fundamental
frequency operation, use the circuit shown in Figure 4. A
parallel-resonant, fundamental frequency, microprocessor-
grade crystal is connected across the CLKIN and XTAL pins.
The on-chip resistance between CLKIN and the XTAL pin is in
the 500 kΩ range. Further parallel resistors are typically not
Table 3. Power Domains
Power Domain
VDD Range
All internal logic and memories
VDDINT
All other I/O
VDDEXT
Power Savings Factor
fCCLKRED
fCCLKNOM
--------------------
VDDINTRED
VDDINTNOM
------------------------
2
TRED
TNOM
------------
=
% Power Savings
1
Power Savings Factor
–
100%
=
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADSP-TS101SAB1-100 | IC DSP CTRLR 128BIT BUS 625BGA |
| ADSP-TS201SYBP-050 | IC PROCESSOR 500MHZ 576-SBGA |
| ADSP-TS202SABPZ050 | IC PROCESSOR 500MHZ 576BGA |
| ADSP-TS203SABP-050 | IC DSP FLOAT/FIXED 500MHZ 576BGA |
| ADUC7021BCPZ62-RL7 | IC MCU 12BIT 1MSPS UART 40-LFCSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-BF592BCPZ-2 | 功能描述:IC DSP CTRLR 64LFCSP 制造商:analog devices inc. 系列:Blackfin? 包裝:托盤 零件狀態(tài):在售 類型:定點(diǎn) 接口:I2C，I2S，IrDA，PPI，SPI，SPORT，UART 時鐘速率:200MHz 非易失性存儲器:ROM（64 kB） 片載 RAM:64KB 電壓 - I/O:1.8V，2.5V，3.3V 電壓 - 內(nèi)核:1.29V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-VFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:64-LFCSP-VQ（9x9） 基本零件編號:ADSP-BF592 標(biāo)準(zhǔn)包裝:1 |
| ADSP-BF592KCPZ | 功能描述:IC DSP CTRLR 64LFCSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:Blackfin® 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-BF592KCPZ-2 | 功能描述:IC DSP CTRLR 200MHZ 64LFCSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:Blackfin® 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-BF606BBCZ-4 | 制造商:Analog Devices 功能描述:BLACKFIN DUAL-CORE PROC W/ 128K SRAM - Trays 制造商:Analog Devices 功能描述:IC DSP CTLR DUAL 349CSPBGA 制造商:Analog Devices 功能描述:IC DSC BLACKFIN DUAL 400MH 制造商:Analog Devices 功能描述:IC, DSC, BLACKFIN, DUAL, 400MHZ, BGA-349 制造商:Analog Devices 功能描述:Blackfin Dual-core Proc W/ 128K SRAM 制造商:Analog Devices 功能描述:IC, DSC, BLACKFIN, DUAL, 400MHZ, BGA-349, Series:Blackfin, No. of Bits:32, Frequ 制造商:Analog Devices 功能描述:IC, DSC, BLACKFIN, DUAL, 400MHZ, BGA-349, Series:Blackfin, No. of Bits:32, Frequency:400MHz, Digital IC Case Style:CSPBGA, No. of Pins:349, Core Supply Voltage Min:1.19V, Core Supply Voltage Max:1.32V, Embedded Interface Type:CAN, 制造商:Analog Devices 功能描述:DSP, FLOATING, 32BIT, 400MHZ, CSPBGA-349, Series:Blackfin, No. of Bits:32 bit, Frequency:400MHz, Digital IC Case Style:CSPBGA, No. of Pins:349, Core Supply Voltage Min:1.19V, Core Supply Voltage Max:1.9V, MSL:- , RoHS Compliant: Yes |
| ADSP-BF606KBCZ-4 | 制造商:Analog Devices 功能描述:BLACKFIN DUAL-CORE PROC W/ 128K SRAM - Trays 制造商:Analog Devices 功能描述:Blackfin Dual-core Proc W/ 128K SRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。