The time tENA_MEASURED is the interval fr" />
參數(shù)資料
型號： ADSP-BF592BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 32/44頁
文件大?。?/td> 0K
描述： IC DSP CTRLR 64LFCSP
視頻文件： Blackfin? BF592 Introduction
特色產(chǎn)品： Blackfin Embedded Processor
標準包裝： 1
系列： Blackfin®
類型： 定點
接口： I²C，I²S，IrDA，PPI，SPI，SPORT，UART
時鐘速率： 400MHz
非易失內(nèi)存： ROM（64 kB）
芯片上RAM： 64kB
電壓 - 輸入/輸出： 1.8V，2.5V，3.3V
電壓 - 核心： 1.29V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應商設備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
Rev. B
|
Page 38 of 44
|
July 2013
The time tENA_MEASURED is the interval from when the reference
signal switches to when the output voltage reaches VTRIP(high)
or VTRIP(low) and is shown below.
VDDEXT (nominal) = 1.8 V, VTRIP (high) is 1.05 V, VTRIP
(low) is 0.75 V
VDDEXT (nominal) = 2.5 V, VTRIP (high) is 1.5 V, VTRIP (low)
is 1.0 V
VDDEXT (nominal) = 3.3 V, VTRIP (high) is 1.9 V, VTRIP (low)
is 1.4 V
Time tTRIP is the interval from when the output starts driving to
when the output reaches the VTRIP(high) or VTRIP(low) trip
voltage.
Time tENA is calculated as shown in the equation:
If multiple pins are enabled, the measurement value is that of
the first lead to start driving.
Output Disable Time Measurement
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The output disable time tDIS is the
difference between tDIS_MEASURED and tDECAY as shown on the left
side of Figure 35.
The time for the voltage on the bus to decay by ΔV is dependent
on the capacitive load CL and the load current IL. This decay
time can be approximated by the equation:
The time tDECAY is calculated with test loads CL and IL, and with
ΔV equal to 0.25 V for VDDEXT (nominal) = 2.5 V/3.3 V and
0.15 V for VDDEXT (nominal) = 1.8V.
The time tDIS_MEASURED is the interval from when the reference
signal switches to when the output voltage decays ΔV from the
measured output high or output low voltage.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose ΔV
to be the difference between the processor’s output voltage and
the input threshold for the device requiring the hold time. CL is
the total bus capacitance (per data line), and IL is the total leak-
age or three-state current (per data line). The hold time will be
tDECAY plus the various output disable times as specified in the
Capacitive Loading
Output delays and holds are based on standard capacitive loads
of an average of 6 pF on all pins (see Figure 36). VLOAD is equal
to (VDDEXT)/2.
The graphs of Figure 37 through Figure 42 show how output
rise time varies with capacitance. The delay and hold specifica-
tions given should be derated by a factor derived from these
figures. The graphs in these figures may not be linear outside the
ranges shown.
tENA
tENA_MEASURED tTRIP
–
=
tDIS
tDIS_MEASURED tDECAY
–
=
tDECAY
CL V
I
L
=
Figure 36. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
Figure 37. Driver Type A Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (1.8V VDDEXT)
T1
ZO = 50
(impedance)
TD = 4.04
r 1.18 ns
2pF
TESTER PIN ELECTRONICS
50
0.5pF
70
400
45
4pF
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
VLOAD
DUT
OUTPUT
50
8
RISE
AND
F
ALL
TIME
(ns)
LOAD CAPACITANCE (pF)
0
50
100
150
250
18
14
0
2
6
12
200
t
RISE
t
FALL
t
FALL = 1.8V @ 25°C
t
RISE = 1.8V @ 25°C
4
10
16
20
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