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參數(shù)資料
| 型號： | ADSP-21MSP58BST-104 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSP Microcomputers |
| 中文描述： | 24-BIT, 13 MHz, OTHER DSP, PQFP100 |
| 封裝： | METRIC, PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 6/40頁 |
| 文件大小： | 372K |
| 代理商： | ADSP-21MSP58BST-104 |
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REV. 0
–6–
ADSP-21msp58/59
CLKIN XTAL
V
CC
GND
A
V
DD
GND
HOST
MODE
CLKOUT
RESET
IRQ2
BR
BG
MMAP
FL0
PMS
RD
WR
ADDRESS
DATA
DMS
BMS
HIP
SERIAL
PORT 0
SERIAL
PORT 1
SCLK
RFS
TFS
DT
DR
SCLK
RFS OR
IRQ0
TFS OR
IRQ1
DT OR FO
DR OR FI
24
14
8
7
3
5
4
4
3
2
1
HIP CONTROL
HIP DATA/ADDR
14
2
8
A
D
CS
OE
BOOT
MEMORY
e.g., EPROM
27C64
27C128
27C256
27C512
A
D
CS
OE
WE
DATA
MEMORY &
PERIPHERALS
(OPTIONAL)
24
16
NOTE: The two MSBs of the Boot EPROM Address are also the two MSBs of the Data Bus.
This is only for the 27C256 and 27C512.
ANALOG
INPUT
ANALOG
OUTPUT
CLOCK OR
CRYSTAL
SERIAL DEVICE
(OPTIONAL)
SERIAL DEVICE
(OPTIONAL)
HOST
PROCESSOR
(OPTIONAL)
A
D
CS
OE
WE
PROGRAM
MEMORY
(OPTIONAL)
D
23-8
D
23-22
D
15-8
ADSP-21msp58/59
Figure 3. ADSP-21msp58/59 Basic System Configuration
CLK OUT signal is enabled and disabled by the CLK ODIS bit
in the SPORT 0 Autobuffer Control Register, DM[0x3FF3].
Because the ADSP-21msp58/59 includes an on-chip oscillator
circuit, an external crystal may also be used. T he crystal should
be connected across the CLK IN and X T AL pins, with two ca-
pacitors connected as shown in Figure 4. A parallel-resonant,
fundamental frequency, microprocessor-grade crystal should be
used.
CLKIN
XTAL
CLKOUT
ADSP-21msp58/59
Figure 4. External Crystal Connections
Reset
T he
RESET
signal initiates a master reset of the ADSP-
21msp58/59. T he
RESET
signal must be asserted during the
power-up sequence to assure proper initialization.
RESET
dur-
ing initial power-up must be held long enough to allow the
processor’s internal clock to stabilize. If
RESET
is asserted at
any time after power-up, the clock continues to run and does
not require stabilization time.
T he power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V
DD
is ap-
plied to the processor and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLK IN cycles will ensure that the PLL has locked (this
does not, however, include the crystal oscillator start-up time).
During this power-up sequence, the
RESET
signal should be
held low. On any subsequent resets, the
RESET
signal must
meet the minimum pulse width specification, t
RSP
.
T he
RESET
input contains some hysteresis; however, if you use
an RC circuit to generate your
RESET
signal, the use of an ex-
ternal Schmidt trigger is recommended.
T he master
RESET
sets all internal stack pointers to the empty
stack condition, masks all interrupts, and clears the MST AT
register. When
RESET
is released, if there is no pending bus re-
quest and the chip is configured for booting (MMAP = 0), the
boot loading sequence is performed. T hen the first instruction is
fetched from internal program memory location 0x0000 and ex-
ecution begins.
Program Memory Interface
T he on-chip program memory address bus (PMA) and on-chip
program memory data bus (PMD) are multiplexed with the on-
chip data memory buses (DMA, DMD), creating a single exter-
nal data bus and a single external address bus. T he data and
address busses are three-stated when the DSP runs from inter-
nal memory. Refer to the
ADSP-2100 Family User’s Manual
,
Chapter 10, “Memory Interface” for a detailed explanation. T he
14-bit address bus directly addresses up to 16K words. See
“Program Memory Maps” for details on program memory
addressing.
T he program memory data lines are bidirectional. T he program
memory select (
PMS
) signal indicates access to program
memory and can be used as a chip select signal. T he write (
WR
)
signal indicates a write operation and is used as a write strobe.
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