參數(shù)資料
型號(hào)： ADSP-21MSP58BST-104
廠商： ANALOG DEVICES INC
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： DSP Microcomputers
中文描述： 24-BIT, 13 MHz, OTHER DSP, PQFP100
封裝： METRIC, PLASTIC, TQFP-100
文件頁(yè)數(shù)： 2/40頁(yè)
文件大?。?/td> 372K
代理商： ADSP-21MSP58BST-104
REV. 0
–2–
ADSP-21msp58/59
DIGIT AL ARCHIT E CT URE OVE RVIE W
Figure 1 is an overall block diagram of the ADSP-21msp58/59.
T he processors contain three independent computational units:
the ALU, the multiplier/accumulator (MAC), and the shifter.
T he computational units process 16-bit data directly and have
provisions to support multiprecision computations. T he ALU
performs a standard set of arithmetic and logic operations; divi-
sion primitives are also supported. T he MAC performs single-
cycle multiply, multiply/add, and multiply/subtract operations.
T he shifter performs logical and arithmetic shifts, normalization,
denormalization, and derive exponent operations. T he shifter
can be used to efficiently implement numeric format control in-
cluding multiword floating-point representations.
T he internal result (R) bus directly connects the computational
units so that the output of any unit may be the input of any unit
on the next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient use of these computational units.
T he sequencer supports conditional jumps, subroutine calls,
and returns in a single cycle. With internal loop counters and
loop stacks, the ADSP-21msp58/59 executes looped code with
zero overhead—no explicit jump instructions are required to
maintain the loop.
T wo data address generators (DAGs) provide addresses for si-
multaneous dual operand fetches (from data memory and pro-
gram memory). Each DAG maintains and updates four address
pointers. Whenever the pointer is used to access data (indirect
addressing), it is post-modified by the value of one of four
modify registers. A length value may be associated with each
pointer to implement automatic modulo addressing for circular
buffers. T he circular buffering feature is also used by the serial
ports for automatic data transfers to (and from) on-chip
memory.
Efficient data transfer is achieved with the use of five internal
buses:
Program Memory Address (PMA) Bus
Program Memory Data (PMD) Bus
Data Memory Address (DMA) Bus
Data Memory Data (DMD) Bus
Result (R) Bus
T he two address buses (PMA, DMA) share a single external ad-
dress bus, allowing memory to be expanded off chip, and the
two data buses (PMD, DMD) share a single external data bus.
T he
BMS
,
DMS
, and
PMS
signals indicate which memory
space the external buses are being used for.
Program memory can store both instructions and data, permit-
ting the ADSP-21msp58/59 to fetch two operands in a single
cycle, one from program memory and one from data memory.
T he ADSP-21msp58/59 can fetch an operand from on-chip
program memory and the next instruction in the same cycle.
T he memory interface supports slow memories and memory-
mapped peripherals with programmable wait state generation.
External devices can gain control of the processors’ buses with
the use of the bus request/grant signals (
BR
and
BG
). Bus grant
has two modes of operation. If GoMode is enabled in the MST AT
register, instruction execution continues from internal memory.
If GoMode is disabled, the processor stops instruction execution
and waits for deassertion of
BR
.
In addition to the address and data bus for external memory
connection, the ADSP-21msp58/59 has a host interface port
(HIP) for easy connection to a host processor. T he HIP is made
up of 8 data/address pins and 10 control pins. T he HIP is ex-
tremely flexible and provides a simple interface to a variety of
host processors. For example, the Motorola 68000 series, the
Intel 80C51 series, and the Analog Devices ADSP-2101 can be
easily connected to the HIP. T he host processor can boot the
ADSP-21msp58/59 on-chip memory through the HIP.
T he ADSP-21msp58/59 can respond to eleven interrupts. T here
can be up to three external interrupts, configured as edge- or
level-sensitive, and seven internal interrupts generated by the
T imer, the Serial Ports (SPORT s), the HIP, the powerdown cir-
cuitry, and the analog interface. T here is also a master
RESET
signal.
T he two serial ports provide a complete synchronous serial in-
terface with optional companding in hardware and a wide vari-
ety of framed or frameless data transmit and receive modes of
operation. Each port can generate an internal programmable se-
rial clock or accept an external serial clock.
Booting circuitry provides for loading on-chip program memory
automatically from byte-wide external memory. After reset,
OUTPUT REGS
INPUT REGS
SHIFTER
OUTPUT REGS
INPUT REGS
ALU
OUTPUT REGS
INPUT REGS
MAC
CLOGIC
16
R BUS
TRANSMIT REG
RECEIVE REG
SERIAL
5
CCIRCUITRY
TRANSMIT REG
RECEIVE REG
SERIAL
5
TIMER
DOWN
CLOGIC
COHIP
AD#1
AD#2
PRROM
(AD4K x 24
PSRAM
2K x 24
DATA
1
8
10
HIP
DATA
EXTERNAL
EXTERNAL
FLAG
DMD BUS
16
24
14
14
PMD BUS
DMA BUS
PMA BUS
PROGRAM
GABOOT
IREGISTER
1
AAND
FILTERS
7
MUX
MUX
14
24
REHIP
Figure 1. ADSP-21msp58/59 Block Diagram
相關(guān)PDF資料
PDF描述
ADSP-BF531 Blackfin Embedded Processor
ADSP-BF531SBBC400 Metal Connector Backshell
ADSP-BF531SBBZ400 Blackfin Embedded Processor
ADSP-BF531SBST400 Circular Connector Series:97
ADSP-BF532 Blackfin Embedded Processor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-3128AJG 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:
ADSP-3128ASG/883B 制造商:Rochester Electronics LLC 功能描述:- Bulk
ADSP-3201JG 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:
ADSP-3201KG 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:MULTIPLIER, 144 Pin, Ceramic, PGA
ADSP-3201TG 制造商:Rochester Electronics LLC 功能描述:- Bulk
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*