參數(shù)資料
型號(hào)： ADSP-21MSP58BST-104
廠商： ANALOG DEVICES INC
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： DSP Microcomputers
中文描述： 24-BIT, 13 MHz, OTHER DSP, PQFP100
封裝： METRIC, PLASTIC, TQFP-100
文件頁(yè)數(shù)： 4/40頁(yè)
文件大小： 372K
代理商： ADSP-21MSP58BST-104
REV. 0
–4–
ADSP-21msp58/59
Pin
Group
Name
#
of
Pins Output Function
Input/
IRQ0
(RFS1)
1
IRQ1
(TFS1)
1
SCLK 1
FI
(DR1)
FO
(DT1)
FL0
V
DD
GND
PWD
Analog Pins
VIN
NORM
I
I
O
I
O
O
External interrupt request #0
External interrupt request #1
Programmable clock output
Flag input pin
Flag output pin
General purpose flag output pin
Digital power supply pins
Ground pins
Powerdown pin
1
1
1
1
4
5
1
I
1
I
Input terminal of the NORM
amplifier for the encoder section
(ADC)
Input terminal of the AUX
amplifier for the encoder section
(ADC)
Ground reference of the NORM
and AUX amplifiers for the
encoder section (ADC)
Noninverting output terminal of
the differential amplifier from
the decoder section (DAC)
Inverting output terminal of the
differential amplifier from the
decoder section (DAC)
Output voltage reference
VIN
AUX
1
I
Decouple
1
I
VOUT
P
1
O
VOUT
N
1
O
V
REF
REF_
FILT ER
1
O
1
O
Voltage reference external by-
pass filter node
Analog power supply
Analog ground
V
CC
GND
A
1
2
Host Interface Port
T he ADSP-21msp58/59 host interface port (HIP) is a parallel
I/O port that allows for an easy connection to a host processor.
T hrough the HIP, the ADSP-21msp58/59 can be used as a
memory-mapped peripheral to a host computer. T he HIP can
be thought of as an area of dual-ported memory, or mailbox reg-
isters, that allows communication between the computational
core of the ADSP-21msp58/59 and the host computer.
T he host interface port is completely asynchronous. T he host
processor can write data into the HIP while the ADSP-
21msp58/59 is operating at full speed.
T he HIP can be configured with the following pins:
BMODE (when MMAP = 0) determines whether the ADSP-
21msp58/59 boots from the host processor (through the HIP)
or external EPROM (through the data bus).
HMD0 configures the bus strobes as separate read and write
strobes, or a single read/write select and a host data strobe.
HMD1 selects separate address (3-bit) and data (8-bit) buses,
or a multiplexed 8-bit address/data bus with address latch
enable.
T ying these pins to appropriate values configures the ADSP-
21msp58/59 for straight-wire interface to a variety of industry-
standard microprocessors and microcomputers.
When the host processor writes an 8-bit value to the HIP, the
upper eight bits of the HIP registers are all zeros. For additional
information, refer to the
ADSP-2100 Family User’s Manual
,
Chapter 7, for information about 8-bit configuration.
HIP Operation
T he HIP contains six data registers (HDR5-0) and two status
registers (HSR7-6) with an associated HMASK register for
masking interrupts from individual HIP data registers. T he HIP
data registers are memory-mapped in the internal data memory
of the ADSP-21msp58/59. HIP transfers can be managed using
either interrupts or polling. T hese registers are shown in the sec-
tion “ADSP-21msp58/59 Registers.” T he two status registers
provide status information to both the ADSP-21msp58/59 and
the host processor. HSR7 contains a software reset bit that can
be set by the ADSP-21msp58/59 and the host.
T he HIP allows a software reset to be performed by the host
processor. T he internal software reset signal is asserted for five
ADSP-21msp58/59 cycles.
T he HIP generates an interrupt whenever an HDR register re-
ceives data from a host processor write. It also generates an in-
terrupt when the host processor has performed a successful read
of any HDR. T he read/write status of the HDRs is also stored in
the HSR registers.
T he HMASK register bits can be used to mask the generation of
read or write interrupts from individual HDR registers. Bits in
the IMASK register enable and disable all HIP read interrupts
or all HIP write interrupts. So, for example, a write to HDR4
will cause an interrupt only if both the
HDR4 Write
bit in
HMASK and the
HIP Write
interrupt enable bit in IMASK are
set.
T he HIP provides a second method of booting the ADSP-
21msp58/59 in which the host processor loads instructions into
the HIP. T he ADSP-21msp58/59 automatically transfers the
data, in this case opcodes, to internal program memory. T he
BMODE pin determines whether the ADSP-21msp58/59 boots
from the host processor through the HIP or from external
EPROM over the data bus.
Interrupts
T he interrupt controller lets the processor respond to interrupts
and reset with a minimum of overhead. T he ADSP-21msp58/59
provides up to three external interrupt input pins,
IRQ0
,
IRQ1
,
and
IRQ2
.
IRQ2
is always available as a dedicated pin;
SPORT 1 may be reconfigured for
IRQ1
and
IRQ0
and the flag.
T he ADSP-21msp58/59 also supports internal interrupts from
the timer, the host interface port, the serial ports, the analog in-
terface, and the powerdown control circuit. T he interrupts are
internally prioritized and individually maskable (except for
powerdown and
RESET
). T he input pins can be programmed
for either level- or edge-sensitivity. T he priorities and vector ad-
dresses for the interrupts are shown in T able II; the interrupt
registers are shown in Figure 2.
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