參數(shù)資料
型號(hào)： ADSP-21990BSTZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 35/50頁(yè)
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 16BIT 176-LQFP
產(chǎn)品變化通告： Product Discontinuance 27/Oct/2011
標(biāo)準(zhǔn)包裝： 1
系列： ADSP-21xx
類型： 定點(diǎn)
接口： SPI，SSP
時(shí)鐘速率： 160MHz
非易失內(nèi)存： 外部
芯片上RAM： 20kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 2.50V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 176-LQFP
供應(yīng)商設(shè)備封裝： 176-LQFP（24x24）
包裝： 托盤
Rev. A
|
Page 40 of 50
|
August 2007
ADSP-21990
POWER DISSIPATION
Total power dissipation has two components, one due to inter-
nal circuitry and one due to the switching of external output
drivers. Internal power dissipation is dependent on the instruc-
tion execution sequence and the data operands involved.
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
Number of output pins that switch during each cycle (O)
The maximum frequency at which they can switch (f)
Their load capacitance (C)
Their voltage swing (VDD)
and is calculated by the formula below.
The load capacitance includes the processor package capaci-
tance (CIN). The switching frequency includes driving the load
high and then back low. Address and data pins can drive high
and low at a maximum rate of 1/(2tCK). The write strobe can
switch every cycle at a frequency of 1/tCK. Select pins switch at
1/(2tCK), but selects can switch on each cycle. For example, esti-
mate PEXT with the following assumptions:
A system with one bank of external data memory—asyn-
chronous RAM (16-bit)
One 64K
16 RAM chip is used with a load of 10 pF
Maximum peripheral speed CCLK = 80 MHz, HCLK =
80 MHz
External data memory writes occur every other cycle, a rate
of 1/(4tHCLK), with 50% of the pins switching
The bus cycle time is 80 MHz (tHCLK = 12.5 ns)
The PEXT equation is calculated for each class of pins that can
drive as shown in Table 16.
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation with
the following formula.
Where:
PEXT is from Table 16.
PINT is IDDINT
2.5 V, using the calculation IDDINT listed in
Note that the conditions causing a worst-case PEXT are different
from those causing a worst-case PINT. Maximum PINT cannot
occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching
simultaneously.
P
EXT
OC
×
V
DD
2
×
f
×
=
P
TOTAL
P
=
EXT
P
INT
+
Table 16. PEXT Calculation Example
Pin Type
Number of Pins
% Switching
C
f
VDD
2
= PEXT
Address
15
50
10 pF
20 MHz
10.9 V
= 0.01635 W
MSx
1
0
10 pF
20 MHz
10.9 V
= 0.0 W
WR
1
10 pF
40 MHz
10.9 V
= 0.00436 W
Data
16
50
10 pF
20 MHz
10.9 V
= 0.01744 W
CLKOUT
1
10 pF
80 MHz
10.9 V
= 0.00872 W
= 0.04687 W
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