參數(shù)資料
型號： ADSP-21990BSTZ
廠商： Analog Devices Inc
文件頁數(shù)： 11/50頁
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 16BIT 176-LQFP
產(chǎn)品變化通告： Product Discontinuance 27/Oct/2011
標(biāo)準(zhǔn)包裝： 1
系列： ADSP-21xx
類型： 定點(diǎn)
接口： SPI，SSP
時(shí)鐘速率： 160MHz
非易失內(nèi)存： 外部
芯片上RAM： 20kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 2.50V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 176-LQFP
供應(yīng)商設(shè)備封裝： 176-LQFP（24x24）
包裝： 托盤
ADSP-21990
Rev. A
|
Page 19 of 50
|
August 2007
SPECIFICATIONS
Specifications subject to change without notice.
RECOMMENDED OPERATING CONDITIONS—ADSP-21990BBC
RECOMMENDED OPERATING CONDITIONS—ADSP-21990BST
Parameter
Conditions
Min
Typ
Max
Unit
VDDINT
Internal (Core) Supply Voltage
2.375
2.5
2.625
V
VDDEXT
External (I/O) Supply Voltage
3.135
3.3
3.465
V
AVDD
Analog Supply Voltage
2.375
2.5
2.625
V
CCLK
DSP Instruction Rate, Core Clock
0
150
MHz
HCLK1, 2
1 The HCLK frequency may be made to appear at the dedicated CLKOUT pin of the device. For low power operation, however, the CLKOUT pin can be disabled.
2 The peripherals operate at the HCLK rate, which may be selected to be equal to CCLK or CCLK
2, up to a maximum of a 75 MHz HCLK for the ADSP-21990BBC.
Peripheral Clock Rate
0
75
MHz
CLKIN3
3 In order to attain the correct CCLK and HCLK values, the input clock frequency or crystal frequency depends on the internal operation of the clock generation PLL
circuit and the associated frequency ratio.
Input Clock Frequency
0
150
MHz
TJUNC
4
4 The maximum junction temperature is limited to 140°C in order to meet all of the electrical specifications. It is ultimately the responsibility of the user to ensure that
the power dissipation of the ADSP-21990 (including all dc and ac loads) is such that the maximum junction temperature limit of 140°C is not exceeded.
Silicon Junction Temperature
140C
C
TAMB
Ambient Operating Temperature
–40C
+85C
C
Parameter
Conditions
Min
Typ
Max
Unit
VDDINT
Internal (Core) Supply Voltage
2.375
2.5
2.625
V
VDDEXT
External (I/O) Supply Voltage
3.135
3.3
3.465
V
AVDD
Analog Supply Voltage
2.375
2.5
2.625
V
CCLK
DSP Instruction Rate, Core Clock
0
160
MHz
HCLK
1, 2
1 The HCLK frequency may be made to appear at the dedicated CLKOUT pin of the device. For low power operation, however, the CLKOUT pin can be disabled.
2 The peripherals operate at the HCLK rate, which may be selected to be equal to CCLK or CCLK/2, up to a maximum of an 80 MHz HCLK for the ADSP-21990BST.
Peripheral Clock Rate
0
80
MHz
CLKIN
3
3 In order to attain the correct CCLK and HCLK values, the input clock frequency or crystal frequency depends on the internal operation of the clock generation PLL
circuit and the associated frequency ratio.
Input Clock Frequency
0
160
MHz
TJUNC
4
4 The maximum junction temperature is limited to 140°C in order to meet all of the electrical specifications. It is ultimately the responsibility of the user to ensure that
the power dissipation of the ADSP-21990 (including all dc and ac loads) is such that the maximum junction temperature limit of 140°C is not exceeded.
Silicon Junction Temperature
140C
C
TAMB
Ambient Operating Temperature
–40C
+85C
C
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ADSP-21991BST 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 160MHz 160MIPS 176-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:HIGH PERFORMANCE MIXED SIGNAL DSP - Bulk
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ADSP-21992BBC 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 150MHz 150MIPS 196-Pin CSP-BGA 制造商:Rochester Electronics LLC 功能描述:MIXED SIGNAL DSP W/32K DM RAM& 16K PMRAM - Bulk
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