參數(shù)資料
型號(hào)： ADSP-2171KST-133
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： DSP Microcomputer
中文描述： 24-BIT, 16.67 MHz, OTHER DSP, PQFP128
封裝： PLASTIC, TQFP-128
文件頁(yè)數(shù)： 2/52頁(yè)
文件大?。?/td> 664K
代理商： ADSP-2171KST-133
REV. A
–2–
ADSP-2171/ADSP-2172/ADSP-2173
Development System
T he ADSP-2100 Family Development Software, a complete set
of toolsfor softwareand hardwaresystem development, supports
the ADSP-217x. T he System Builder provides a high-level
method for defining the architecture of systems under develop-
ment. T heAssembler hasan algebraic syntax that iseasy to
program and debug. T he Linker combines object files into
an executable file. T he Simulator provides an interactive
instruction-level simulation with a reconfigurable user interface
to display different portions of the hardware environment. A
PROM Splitter generates PROM programmer compatible files.
T he C Compiler, based on the Free Software Foundation’s
GNU C Compiler, generates ADSP-217x assembly source
code. T he Runtime Library includes over 100 ANSI-standard
mathematical and DSP-specific functions.
EZ-T ools, low cost, easy-to-use hardware tools, also support the
ADSP-217x.
T he ADSP-217x EZ-ICE
Emulator aids in the hardware de-
bugging of ADSP-217x systems. T he emulator consists of hard-
ware, host computer resident software, the emulator probe, and
the pin adaptor. T he emulator performs a full range of emula-
tion functions including stand-alone operation or operation in
the target, setting up to 20 breakpoints, single-step or full-speed
operation in the target, examining and altering registers and
memory values, and PC upload/download functions. If you plan
to use the emulator, you should consider the emulator’s restric-
tions (differences between emulator and processor operation).
T he EZ-LAB
Evaluation Board is a PC plug-in card, but it can
operate in stand-alone mode. T he evaluation board/system de-
velopment board executes EPROM-based or downloaded pro-
grams. Modular Analog Front End daughter cards with different
codecs will be made available.
EZ-ICE and EZ-LAB are registered trademarks of Analog Devices, Inc.
Additional Information
T his data sheet provides a general overview of ADSP-217x
functionality. For additional information on the architecture and
instruction set of the processor, refer to the
ADSP-2100 Family
User’s Manual
. For more information about the Development
System and ADSP-217x programmer’s reference information,
refer to the
ADSP-2100 Family Assembler Tools & Simulator
Manual
.
ARCHIT E CT URE OVE RVIE W
Figure 1 is an overall block diagram of the ADSP-217x. T he
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC) and the shifter. T he
computational units process 16-bit data directly and have provi-
sions to support multiprecision computations. T he ALU per-
forms a standard set of arithmetic and logic operations; division
primitives are also supported. T he MAC performs single-cycle
multiply, multiply/add and multiply/subtract operations with
40 bits of accumulation. T he shifter performs logical and
arithmetic shifts, normalization, denormalization, and derive
exponent operations. T he shifter can be used to efficiently
implement numeric format control including multiword and
block floating-point representations.
T he internal result (R) bus directly connects the computational
units so that the output of any unit may be the input of any unit
on the next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu-
tational units. T he sequencer supports conditional jumps, sub-
routine calls and returns in a single cycle. With internal loop
counters and loop stacks, the ADSP-217x executes looped code
with zero overhead; no explicit jump instructions are required to
maintain the loop.
Figure 1. ADSP-217x Block Diagram
R BUS
16
HIP
CONTROL
HIP
REGISTERS
BOOT
ADDRESS
GENERATOR
BUS
EXCHANGE
COMPANDING
CIRCUITRY
DMA BUS
PMA BUS
DMD BUS
PMD BUS
PROGRAM
SEQUENCER
INSTRUCTION
REGISTER
DATA
ADDRESS
GENERATOR
#2
DATA
ADDRESS
GENERATOR
#1
14
14
INPUT REGS
OUTPUT REGS
SHIFTER
INPUT REGS
OUTPUT REGS
MAC
INPUT REGS
OUTPUT REGS
ALU
24
16
5
16
MUX
24
MUX
SERIAL
PORT 0
RECEIVE REG
TRANSMIT REG
CONTROL
LOGIC
DATA
SRAM
2K X 16
POWER DOWN
CONTROL
LOGIC
14
TIMER
2
3
11
HIP
DATA
BUS
PROGRAM ROM
8K X 24
PROGRAM SRAM
2K X 24
SERIAL
PORT 1
RECEIVE REG
TRANSMIT REG
FLAGS
EXTERNAL
DATA
BUS
EXTERNAL
ADDRESS
BUS
5
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