參數(shù)資料
型號: ADSP-2171KST-133
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號處理
英文描述: DSP Microcomputer
中文描述: 24-BIT, 16.67 MHz, OTHER DSP, PQFP128
封裝: PLASTIC, TQFP-128
文件頁數(shù): 19/52頁
文件大小: 664K
代理商: ADSP-2171KST-133
ADSP-2171/ADSP-2172/ADSP-2173
REV. A
–19–
ADSP-2171/ADSP-2172
Parameter
Min
Max
Unit
Clock Signals
t
CK
is defined as 0.5 t
CK I.
T he ADSP-2171/ADSP-2172 uses an
input clock with a frequency equal to half the instruction rate; a
clock (which is equivalent to 60 ns) yields a 30 ns processor cycle
16.67 MHz input (equivalent to 33 MHz). t
CK
values within the
range of 0.5 t
CK I
period should be substituted for all relevant
timing parameters to obtain specification value.
Example: t
CK H
= 0.5t
CK
– 7 ns = 0.5 (30 ns) – 7 ns = 8 ns.
T iming Requirement:
t
CK I
t
CK IL
t
CK IH
CLK IN Period
CLK IN Width Low
CLK IN Width High
60
20
20
150
ns
ns
ns
Switching Characteristic:
t
CK L
t
CK H
t
CK OH
CLK OUT Width Low
CLK OUT Width High
CLK IN High to CLK OUT High
0.5t
CK
– 7
0.5t
CK
– 7
0
ns
ns
ns
20
Control Signals
T iming Requirement:
t
RSP
RESET Width Low
5t
CK1
ns
NOT E
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLK IN cycles assuming stable CLK IN (not including crystal
oscillator start-up time).
CLKIN
CLKOUT
t
CKIL
t
CKOH
t
CKH
t
CKL
t
CKI
t
CKIH
Figure 8. Clock Signals
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參數(shù)描述
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