參數(shù)資料
型號: ADSP-2105BP-80
廠商: Analog Devices Inc
文件頁數(shù): 26/64頁
文件大?。?/td> 0K
描述: IC DSP CONTROLLER 16BIT 68PLCC
標準包裝: 19
系列: ADSP-21xx
類型: 定點
接口: 同步串行端口(SSP)
時鐘速率: 20MHz
非易失內(nèi)存: 外部
芯片上RAM: 3kB
電壓 - 輸入/輸出: 5.00V
電壓 - 核心: 5.00V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 68-LCC(J 形引線)
供應商設備封裝: 68-PLCC(24.23x24.23)
包裝: 管件
ADSP-21xx
–32–
REV. B
Frequency
13 MHz
13.824 MHz 16.67 MHz
20 MHz
25 MHz
Dependency
Parameter
Min Max Min Max
Min Max
Min Max Min Max Min
Max
Unit
Timing Requirement:
tBH
BR Hold after CLKOUT High
1
24.2
23.1
20
17.5
15
0.25tCK + 5
ns
tBS
BR Setup before CLKOUT Low
1
39.2
38.1
35
32.5
30
0.25tCK + 20
ns
Switching Characteristic:
tSD
CLKOUT High to DMS,
39.2
38.1
35
32.5
30
0.25tCK + 20 ns
PMS, BMS, RD, WR Disable
tSDB DMS, PMS, BMS, RD, WR
00
0
000
ns
Disable to BG Low
tSE
BG High to DMS, PMS,
0
ns
BMS, RD, WR Enable
tSEC DMS, PMS, BMS, RD, WR
9.2
8.1
5
2.5
1.5
2
0.25tCK – 10
2
ns
Enable to CLKOUT High
NOTES
1If BR meets the t
BS and tBH setup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cycle. BR requires
a pulse width greater than 10 ns.
2For 25 MHz only the minimum frequency dependency formula for t
SEC = (0.25tCK – 8.5).
Section 10.2.4, “Bus Request/Grant,” on page 212 of the
ADSP-2100 Family User’s Manual (1st Edition, 1993) states that “When BR is recognized, the processor
responds immediately by asserting BG during the same cycle.” This is incorrect for the current versions of all ADSP-21xx processors: BG is asserted in the cycle after
BR is recognized. No external synchronization circuit is needed when BR is generated as an asynchronous signal.
TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163)
BUS REQUEST/GRANT
CLKOUT
PMS, DMS
BMS, RD
WR
t
BS
BR
BG
CLKOUT
t
SD
t
SDB
t
SE
t
SEC
t
BH
Figure 31. Bus Request/Grant
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