V
參數(shù)資料
型號(hào)： ADSP-2105BP-80
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 14/64頁(yè)
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 16BIT 68PLCC
標(biāo)準(zhǔn)包裝： 19
系列： ADSP-21xx
類型： 定點(diǎn)
接口： 同步串行端口（SSP）
時(shí)鐘速率： 20MHz
非易失內(nèi)存： 外部
芯片上RAM： 3kB
電壓 - 輸入/輸出： 5.00V
電壓 - 核心： 5.00V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 68-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 68-PLCC（24.23x24.23）
包裝： 管件
ADSP-2111–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
K Grade
B Grade
T Grade
Parameter
Min
Max
Min
Max
Min
Max
Unit
VDD
Supply Voltage
4.50
5.50
4.50
5.50
4.50
5.50
V
TAMB
Ambient Operating Temperature
0
+70
–40
+85
–55
+125
°C
See “Environmental Conditions” for information on thermal specifications.
ELECTRICAL CHARACTERISTICS
Parameter
Test Conditions
Min
Max
Unit
VIH
Hi-Level Input Voltage
3, 5
@ VDD = max
2.0
V
VIH
Hi-Level CLKIN Voltage
@ VDD = max
2.2
V
VIL
Lo-Level Input Voltage
1, 3
@ VDD = min
0.8
V
VOH
Hi-Level Output Voltage
2, 3, 7
@ VDD = min, IOH = –0.5 mA
2.4
V
@ VDD = min, IOH = –100
A8
VDD – 0.3
V
VOL
Lo-Level Output Voltage
2, 3, 7
@ VDD = min, IOL = 2 mA
0.4
V
IIH
Hi-Level Input Current
1
@ VDD = max, VIN = VDD max
10
A
IIL
Lo-Level Input Current
1
@ VDD = max, VIN = 0V
10
A
IOZH
Tristate Leakage Curren
4
@ VDD = max, VIN = VDD max
6
10
A
IOZL
Tristate Leakage Current
4
@ VDD = max, VIN = 0V
6
10
A
CI
Input Pin Capacitance
1, 8, 9
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25
°C8
pF
CO
Output Pin Capacitance
4, 8, 9, 10
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25
°C8
pF
NOTES
1Input-only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR1, DR0, HSEL, HSIZE, BMODE, HMD0, HMD1, HRD/HRW, HWR/HDS, HA2/ALE, HA1-0.
2Output pins: BG, PMS, DMS, BMS, RD, WR, A0–A13, CLKOUT, DT1, DT0, HACK, FL2-0.
3Bidirectional pins: D0–D23, SCLK1, RFS1, TFS1, SCLK0, RFS0, TFS0, HD0–HD15/HAD0–HAD15.
4Tristatable pins: A0–A13, D0–D23, PMS, DMS, BMS, RD, WR, DT1, SCLK1, RSF1, TFS1, DT0, SCLK0, RFS0, TFS0, HD0–HD15/HAD0–HAD15.
5Input-only pins: RESET, IRQ2, BR, MMAP, DR1, DR0, HSEL, HSIZE, BMODE, HMD0, HMD1, HRD/HRW, HWR/HDS, HA2/ALE, HA1-0.
6 0 V on BR, CLKIN Active (to force tristate condition).
7Although specified for TTL outputs, all ADSP-2111 outputs are CMOS-compatible and will drive to V
DD and GND, assuming no dc loads.
8Guaranteed but not tested.
9Applies to ADSP-2111 PGA and PQFP packages.
10Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
DD + 0.3 V
Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to V
DD + 0.3 V
Operating Temperature Range (Ambient) . . . –55C to +125C
Storage Temperature Range . . . . . . . . . . . . . –65C to +150C
Lead Temperature (10 sec) PGA . . . . . . . . . . . . . . . . . +300C
Lead Temperature (5 sec) PQFP . . . . . . . . . . . . . . . . . +280C
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these
or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
ADSP-21xx
REV. B
–21–
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