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| 型號： | ADS1271EVM |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | modular EVM form factor |
| 中文描述： | 模塊化EVM的外形 |
| 文件頁數(shù)： | 22/29頁 |
| 文件大小： | 381K |
| 代理商： | ADS1271EVM |
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SBAS306A NOVEMBER 2004 REVISED DECEMBER 2004
www.ti.com
22
PHASE RESPONSE
The ADS1271 incorporates a multiple stage, linear phase
digital filter. Linear phase filters exhibit constant delay time
versus input frequency (constant group delay). This
means the time delay from any instant of the input signal
to the same instant of the output data is constant and is
independent of input signal frequency. This behavior
results in essentially zero phase errors when analyzing
multi-tone signals.
SETTLING TIME
As with frequency and phase response, the digital filter
also determines settling time. Figure 56 shows the output
settling behavior after a step change on the analog inputs
normalized to conversion periods. The X axis is given in
units of conversion. Note that after the step change on the
input occurs, the output data changes very little prior to 30
conversion periods. The output data is fully settled after 76
conversion periods for High-Speed and Low-Power
modes, and 78 conversions for High-Resolution mode.
100
0
%
Conversions (1/f
DATA
)
0
20
10
40
30
60
50
80
70
Fully Settled Data
at 76 Conversions
(78 Conversions for
HighResolution mode)
Initial Value
Final Value
Figure 56. Settling Time for All Power Modes
DATA FORMAT
The ADS1271 outputs 24 bits of data in two’s complement
format.
A positive full-scale input produces an output code of
7FFFFFh, and the negative full-scale input produces an
output code of 800000h. The output clips at these codes
for signals exceeding full-scale. Table 9 summarizes the
ideal output codes for different input signals.
Table 9. Ideal Output Code versus Input Signal
INPUT SIGNAL VIN
(AINP AINN)
IDEAL OUTPUT CODE(1)
+V
REF
+V
REF
2
23
0
7FFFFFh
1
000001h
000000h
V
REF
2
23
1
FFFFFFh
V
REF
2
23
2
23
1
800000h
(1)Excludes effects of noise, INL, offset and gain errors.
SERIAL INTERFACE
Data is retrieved from the ADS1271 using the serial
interface. To provide easy connection to either
microcontrollers or DSPs, two formats are available for the
interface: SPI and Frame-Sync. The FORMAT pin selects
the interface. The same pins are used for both interfaces
(SCLK, DRDY/FSYNC, DOUT and DIN), though their
respective functionality depends on the particular interface
selected.
SPI SERIAL INTERFACE
The SPI-compatible format is a simple read-only interface.
Data ready for retrieval is indicated by the DRDY output
and is shifted out on the falling edge of SCLK, MSB first.
The interface can be daisy-chained using the DIN input
when using multiple ADS1271s. See the
Daisy-Chaining
section for more information.
SCLK (SPI Format)
The serial clock (SCLK) features a Schmitt-triggered input
and shifts out data on DOUT on the falling edge. It also
shifts in data on the falling edge on DIN when this pin is
being used for daisy-chaining. The device shifts data out
on the falling edge and the user shifts this data in on the
rising edge. Even though the SCLK input has hysteresis,
it is recommended to keep SCLK as clean as possible to
prevent glitches from accidentally shifting the data. SCLK
should be held low after data retrieval. SCLK may be run
as fast as the CLK frequency. SCLK may be either in
free-running
or
stop-clock
conversions. To maximize the converter performance, the
ratio of CLK to SCLK should be held to:
operation
between
SCLK
CLK
2
N
N
0,1,2
.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS1271EVM-PDK | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS1271 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| ADS1271IBPW | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24B 105kSPS Indus Delta-Sigma ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1271IBPW | 制造商:Texas Instruments 功能描述:24BIT ADC 105KSPS DELTA S 16TSSOP 制造商:Texas Instruments 功能描述:24BIT ADC, 105KSPS, DELTA S, 16TSSOP 制造商:Texas Instruments 功能描述:24BIT ADC, 105KSPS, DELTA S, 16TSSOP; Resolution (Bits):24bit; Sampling Rate:105kSPS; Supply Voltage Type:Single; Supply Voltage Min:4.75V; Supply Voltage Max:5.25V; Supply Current:17mA; Digital IC Case Style:TSSOP; No. of Pins:16; ;RoHS Compliant: Yes |
| ADS1271IBPWG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24B 105kSPS Indus Delta-Sigma ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1271IBPWR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24B 105kSPS Indus Delta-Sigma ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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