參數(shù)資料
型號(hào): ADS1271EVM
廠商: Texas Instruments, Inc.
英文描述: modular EVM form factor
中文描述: 模塊化EVM的外形
文件頁(yè)數(shù): 17/29頁(yè)
文件大小: 381K
代理商: ADS1271EVM
SBAS306A NOVEMBER 2004 REVISED DECEMBER 2004
www.ti.com
17
MODE SELECTION (MODE)
The ADS1271 supports three modes of operation:
High-Speed, High-Resolution, and Low-Power. The mode
selection is determined by the status of the digital input
MODE pin, as shown in Table 5. A high impedance, or
floating,
condition allows the MODE pin to support a third
state. The ADS1271 constantly monitors the status of the
MODE pin during operation and responds to a change in
status after 12,288 CLK periods. When floating the MODE
pin, keep the total capacitance on the pin less than 100pF
and the resistive loading greater than 10M
to ensure
proper operation. Changing the mode clears the internal
offset calibration value. If onboard offset calibration is
being used, be sure to recalibrate after a mode change.
When daisy-chaining multiple ADS1271s together and
operating in High-Resolution mode (MODE pin floating), the
MODE pin of each device must be isolated from one another;
this ensures proper device operation. The MODE pins can be
tied together for High-Speed and Low-Power modes.
Table 5. Mode Selection
MODE PIN STATUS
MODE SELECTION
Logic Low (DGND)
Floating(1)
High-Speed
High-Resolution
Logic High (DVDD)
Low-Power
(1)Load on MODE: C < 100pF, R > 10M
When using the SPI format, DRDY is held high after a
mode change occurs until settled (or valid) data is ready,
as shown in Figure 43.
In Frame-Sync format, the DOUT pin is held low after a
mode change occurs until settled data is ready, as shown
in Figure 43. Data can be read from the device to detect
when DOUT changes to logic 1, indicating valid data.
FORMAT SELECTION (FORMAT)
To help connect easily to either microcontrollers or DSPs,
the ADS1271 supports two formats for the serial interface:
an SPI-compatible interface and a Frame-Sync interface.
The format is selected by the FORMAT pin, as shown in
Table 6. It is recommended that the FORMAT pin be
directly tied to the appropriate voltage. If the status of this
pin changes, perform a Sync operation afterwards to
ensure proper operation.
Table 6. Format Selection
FORMAT PIN STATUS
SERIAL INTERFACE FORMAT
Logic Low (DGND)
SPI
Logic High (DVDD)
Frame-Sync
MODE
Pin
ADS1271
Mode
HighSpeed
SYMBOL
t
MD
Time to register MODE changes
CLK periods
t
NDR
Time for new data to be ready
128
Conversions
(1/f
DATA
)
MIN
TYP
MAX
UNITS
DESCRIPTION
LowPower
LowPower Mode
Valid Data Ready
DRDY
SPI
Format
FrameSync
Format
CLK
t
MD
DOUT
LowPower Mode
Valid Data on DOUT
t
NDR
t
NDR
12,288
Figure 43. Mode Change Timing
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