參數(shù)資料
型號： ADS1259EVM
廠商： Texas Instruments
文件頁數(shù)： 24/48頁
文件大?。?/td> 0K
描述： EVAL MODULE FOR ADS1259
標準包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 14k
數(shù)據(jù)接口： 串行，SPI?
工作溫度： -40°C ~ 125°C
已用 IC / 零件： ADS1259
已供物品： 板
其它名稱： 296-29312
ADS1259EVM-ND
SCLK
DRDY
t
DRSC
t
SCDR
1
9
17
25
33
DRDY
(1)
CS
(2)
SCLK
(3)
DOUT
DATAMSB
DATAMID
DATALSB
CHECKSUM
(6)
DATAMSB
(7)
DIN
(8)
DataReady
NextDataReady
t
UPDATE
(4)
Hi-Z
(5)
SBAS424D
– JUNE 2009 – REVISED AUGUST 2011
DATA RETRIEVAL
The Read Data Continuous mode is cancelled by
sending the Stop Read Data Continuous command
New conversion data are available when DRDY goes
(SDATAC). This operation occurs simultaneously with
low. Read the data within 20 fCLK cycles of the next
ADC conversion data on DOUT which can be
DRDY falling edge or the data are incorrect. Do not
ignored. Once the SDATAC command is sent, other
read data during this interval. The conversion data
commands may be sent to the ADS1259. Observe
may be read in two ways: Data Read in Continuous
the SCLK and DRDY timing requirements, when
mode and Data Read in Stop Continuous mode.
reading data in this mode, as shown in Figure 59 and
Data Read Operation in Continuous Mode
In Read Data Continuous mode the conversion data
may be shifted out directly without the need of the
data read command. When DRDY (and DOUT, if CS
is low) assert low, the conversion data are ready. The
data are shifted out on DOUT on the rising edges of
SCLK, with the most significant bit (MSB) clocked out
first. In Gate Convert Mode, DRDY returns to high on
Figure 59. SCLK to DRDY Timing
the first falling edge of SCLK. In Pulse Convert mode,
DRDY remains low until a new conversion starts.
As shown in Figure 60, the conversion data consist of
Table 18. SCLK and DRDY Timing Characteristics
three or four bytes (data MSB first), depending on
for Figure 57
whether the checksum byte is included. The data
SYMBOL
DESCRIPTION
MIN
UNIT
may be read multiple times by continuing to shift the
tSCDR
SCLK low before DRDY
data. The data read operation must be completed
20
tCLK
low(1)
with 20 fCLK cycles of next DRDY falling edge.
tDRSC
DRDY falling edge to SCLK
40
ns
rising edge(1)
(1) These requirements apply only to reading conversion data in
RDATAC mode.
(1) In Gate Convert Conversion mode, DRDY returns to high on the first falling edge of SCLK. In Pulse Convert mode, DRDY remains low
until the next conversion is started.
(2) CS may be held low. If CS is low, DOUT asserts low with DRDY.
(3) Data are updated on the rising edge of SCLK. DOUT is low until the first rising edge of SCLK.
(4) tUPDATE = 20/fCLK. Do not read data during this time.
(5) During this interval, DOUT follows DRDY.
(6) Optional data checksum byte.
(7) Optional repeat of previous conversion data.
(8) Hold DIN low, except for transmission of the SDATAC (STOP Read Data Continuous command).
Figure 60. Data Read Operation in Continuous Mode
30
Copyright
2009–2011, Texas Instruments Incorporated
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADS1259EVM 制造商:Texas Instruments 功能描述:DEVELOPMENT TOOL
ADS1259EVM-PDK 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS1259 Perf Demo Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
ADS1259EVM-PDK 制造商:Texas Instruments 功能描述:DEVELOPMENT TOOL
ADS1259IPW 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Low-Noise 14kSPS 24B ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS1259IPW 制造商:Texas Instruments 功能描述:A/D CONVERTER (A-D) IC
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