參數(shù)資料
型號： ADS1259EVM
廠商： Texas Instruments
文件頁數(shù)： 10/48頁
文件大?。?/td> 0K
描述： EVAL MODULE FOR ADS1259
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 14k
數(shù)據(jù)接口： 串行，SPI?
工作溫度： -40°C ~ 125°C
已用 IC / 零件： ADS1259
已供物品： 板
其它名稱： 296-29312
ADS1259EVM-ND
H
=
H
(f)
H
(f)
=
(f)
sinc
5
N
5
sin
512
f
p
f
CLK
64
sin
8
f
p
f
CLK
sin
512
R
f
p
f
CLK
R
sin
512
f
p
f
CLK
N
Analog
Modulator
sinc
5
Filter
(decimateby64)
sinc Filter
1
f
/512
CLK
ModulatorRate=f
/8
CLK
sinc Filter
2
DR[2:0]RegisterBits
(ProgramDecimation)
Output
DataRate=f
/(R
)
CLK
512
SINC2RegisterBit
(0=sinc )
1
SBAS424D
– JUNE 2009 – REVISED AUGUST 2011
DIGITAL FILTER
The SINC2 register bit selects either the sinc1 or sinc2
filter. The sinc1 filter settles in one conversion cycle
The programmable low-pass digital filter receives the
while the sinc2 filter settles in two conversion cycles.
modulator output and produces a high-resolution
However, the sinc2 filter has the benefit of wider
digital output. By adjusting the amount of filtering,
frequency notches which improve line cycle rejection.
tradeoffs can be made between resolution and data
rate: filter more for higher resolution, filter less for
FREQUENCY RESPONSE
higher data rate.
The low-pass digital filter sets the overall frequency
The filter consists of two sections: a fixed decimation
response of the ADS1259. The filter response is the
sinc5 filter followed by a variable decimation filter,
product of the fixed and programmable filter sections,
configurable as sinc1 or sinc2, as illustrated in
and is given by Equation 5:
Figure 39. The sinc5 filter has fixed decimation of 64
and reduces the data rate of the modulator from
fCLK/8 to fCLK/512. The second filter stage receives the
data from the sinc5 filter. The second filter stage has
programmable averaging (or decimation) and can be
configured in either sinc1 or sinc2 mode. The
decimation ratio of this stage sets the final output
data rate. As detailed in Table 3, the DR[2:0] register
bits program the decimation ratio and the final output
data rate. The output data rates are identical for both
where:
sinc1 and sinc2 filters.
N = 1 (sinc1)
Table 3. Decimation Ratio of Final Filter Stage
N = 2 (sinc2)
R = Decimation ratio (refer to Table 3)
(5)
DR[2:0] REGISTER
DECIMATION
BITS
RATIO (R)
DATA RATE (SPS)
The digital filter attenuates noise on the modulator
111
1
14400
output, including noise from within the ADS1259 and
110
4
3600
external noise present within the ADS1259 input
101
12
1200
signal.
Adjusting
the
filtering
by
changing
the
decimation ratio used in the programmable filter
100
36
400
changes the filter bandwidth. With a higher number of
011
240
60
decimation, the bandwidth is reduced and more noise
010
288
50
is attenuated.
001
864
16.6
000
1440
10
Figure 39. Block Diagram of Digital Filter
18
Copyright
2009–2011, Texas Instruments Incorporated
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADS1259EVM 制造商:Texas Instruments 功能描述:DEVELOPMENT TOOL
ADS1259EVM-PDK 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS1259 Perf Demo Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
ADS1259EVM-PDK 制造商:Texas Instruments 功能描述:DEVELOPMENT TOOL
ADS1259IPW 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Low-Noise 14kSPS 24B ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS1259IPW 制造商:Texas Instruments 功能描述:A/D CONVERTER (A-D) IC
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