參數(shù)資料
型號： ADS1256IDBR
英文描述： Very Low Noise, 24-Bit Analog-to-Digital Converter
中文描述： 極低噪聲，24位模擬數(shù)字轉(zhuǎn)換器
文件頁數(shù)： 3/39頁
文件大小： 427K
代理商： ADS1256IDBR
SBAS288D JUNE 2003 REVISED AUGUST 2004
www.ti.com
3
ELECTRICAL CHARACTERISTICS
All specifications at 40
°
C to +85
°
C, AVDD = +5V, DVDD = +1.8V, fCLKIN = 7.68MHz, PGA = 1, and VREF = +2.5V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
Analog Inputs
Full-scale input voltage (AINP AINN)
Buffer off
Absolute input voltage
(AIN0-7, AINCOM to AGND)
Buffer on
Programmable gain amplifier
Buffer off, PGA = 1, 2, 4, 8, 16
Buffer off, PGA = 32, 64
Buffer on, fDATA
≤
50Hz(1)
SDCS[1:0] = 01
SDCS[1:0] = 10
SDCS[1:0] = 11
System Performance
Resolution
No missing codes
All data rates and PGA settings
Data rate (fDATA)
fCLKIN = 7.68MHz
Differential input, PGA = 1
Differential input, PGA = 64
Offset error
After calibration
PGA = 1
PGA = 64
After calibration, PGA = 1, Buffer on
After calibration, PGA = 64, Buffer on
PGA = 1
PGA = 64
Common-mode rejection
fCM(4) = 60Hz, fDATA = 30kSPS(5)
Noise
AVDD power-supply rejection
±
5%
in AVDD
DVDD power-supply rejection
±
10%
in DVDD
Voltage Reference Inputs
Reference input voltage (VREF)
VREF
≡
VREFP VREFN
Buffer off
Buffer on(6)
Buffer off
Buffer on(6)
Voltage reference impedance
fCLKIN = 7.68MHz
Digital Input/Output
DIN, SCLK, XTAL1/CLKIN,
SYNC/PDWN, CS, RESET
D0/CLKOUT, D1, D2, D3
VIL
VOH
IOH = 5mA
VOL
IOL = 5mA
Input hysteresis
Input leakage
0 < VDIGITAL INPUT < DVDD
External crystal between XTAL1 and
XTAL2
External oscillator driving CLKIN
MIN
TYP
MAX
UNIT
±
2VREF/PGA
V
V
V
AGND 0.1
AGND
1
AVDD + 0.1
AVDD 2.0
64
150/PGA
4.7
80
0.5
2
10
k
k
M
μ
A
μ
A
μ
A
Differential input impedance
Sensor detect current sources
24
24
2.5
Bit
Bit
30,000
±
0.0010
SPS(2)
%FSR(3)
%FSR
Integral nonlinearity
±
0.0003
±
0.0007
On the level of the noise
±
100
±
4
±
0.005
±
0.03
±
0.8
±
0.8
110
See Noise Performance Tables
70
100
Offset drift
nV/
°
C
nV/
°
C
%
%
ppm/
°
C
ppm/
°
C
dB
Gain error
Gain drift
95
60
dB
dB
0.5
2.5
2.6
V
V
V
V
V
k
Negative reference input (VREFN)
AGND 0.1
AGND
VREFN + 0.5
VREFN + 0.5
VREFP 0.5
VREFP 0.5
AVDD + 0.1
AVDD 2.0
Positive reference input (VREFP)
18.5
VIH
0.8 DVDD
5.25
V
0.8 DVDD
DGND
0.8 DVDD
DVDD
0.2 DVDD
V
V
V
V
V
μ
A
0.2 DVDD
0.5
±
10
Master clock rate
2
7.68
10
MHz
0.1
7.68
10
MHz
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