- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375263 > ADS1256IDBR Very Low Noise, 24-Bit Analog-to-Digital Converter PDF資料下載
參數(shù)資料
| 型號： | ADS1256IDBR |
| 英文描述： | Very Low Noise, 24-Bit Analog-to-Digital Converter |
| 中文描述： | 極低噪聲，24位模擬數(shù)字轉換器 |
| 文件頁數(shù)： | 27/39頁 |
| 文件大?。?/td> | 427K |
| 代理商： | ADS1256IDBR |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當前第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁
SBAS288D JUNE 2003 REVISED AUGUST 2004
www.ti.com
27
DATA READY (DRDY
)
The DRDY output is used as a status signal to indicate
when conversion data is ready to be read. DRDY goes low
when new conversion data is available. It is reset high
when all 24 bits have been read back using Read Data
(RDATA) or Read Data Continuous (RDATAC) command.
It also goes high when the new conversion data is being
updated. Do not retrieve during this update period as the
data is invalid. If data is not retrieved, DRDY will only be
high during the update time as shown in Figure 24.
Data Updating
DRDY
Figure 24. DRDY with No Data Retreival
After changing the PGA, data rate, buffer status, writing to
the OFC or FSC registers, and enabling or disabling the
sensor detect circuitry, perform a synchronization
operation to force DRDY high. It will stay high until valid
data is ready. If auto-calibration is enabled (by setting the
ACAL bit in the ADCON register), DRDY will go low after
the self-calibration is complete and new data is valid.
Exiting from Reset, Synchronization, Standby or
Power-Down mode will also force DRDY high. DRDY will
go low as soon as valid data is ready.
SYNCHRONIZATION
Synchronization of the ADS1255/6 is available to
coordinate the A/D conversion with an external event and
also to speed settling after an instantaneous change on
the analog inputs (see Conversion Time using
Synchronization section).
Synchronization can be achieved either using the
SYNC/PDWN pin or with the SYNC command. To use the
SYNC/PDWN pin, take it low and then high, making sure
to meet timing specification t
16
. Synchronization occurs on
the first rising edge of the master clock after SYNC/PDWN
is taken high. No communication is possible on the serial
interface while SYNC/PDWN is low. If the SYNC/PDWN
pin is held low for 20 DRDY periods the ADS1255/6 will
enter Power-Down mode.
To synchronize using the SYNC command, first shift in all
eight bits of the SYNC command. This stops the operation
of the ADS1255/6. When ready to synchronize, issue the
WAKEUP command. Synchronization occurs on the first
rising edge of the master clock after the first SCLK used to
shift in the WAKEUP command. After a synchronization
operation, either with the SYNC/PDWN pin or the SYNC
command, DRDY stays high until valid data is ready.
STANDBY MODE
The standby mode shuts down all of the analog circuitry
and most of the digital features. The oscillator continues to
run to allow for fast wakeup. If enabled, clock output
D0/CLKOUT will also continue to run during during
Standby mode. To enter Standby mode, issue the
STANDBY command. To exit Standby mode, issue the
WAKEUP command. DRDY will stay high after exiting
Standby mode until valid data is ready. Standby mode can
be used to perform one-shot conversions; see Settling
Time Using One-Shot Mode section for more details.
POWER-DOWN MODE
Holding the SYNC/PDWN pin low for 20 DRDY cycles
activates the Power-Down mode. During Power-Down
mode, all circuitry is disabled including the oscillator and
the clock output.
To exit Power-Down mode, take the SYNC/PDWN pin
high. Upon exiting from Power-Down mode, the
ADS1255/6 crystal oscillator typically requires 30ms to
wake up. If using an external clock source, 8192 CLKIN
cycles are needed before conversions begin.
RESET
There are three methods to reset the ADS1255/6: the
RESET input pin, RESET command, and a special SCLK
reset pattern.
When using the RESET pin, take it low to force a reset.
Make sure to follow the minimum pulse width timing
specifications before taking the RESET pin back high.
The RESET command takes effect after all eight bits have
been shifted into DIN. Afterwards, the reset releases
automatically.
The ADS1255/6 can also be reset with a special pattern on
SCLK (see Figure 2). Reset occurs on the falling edge of
the last SCLK edge in the pattern. After performing the
operation, the reset releases automatically.
On reset, the configuration registers are initialized to their
default state except for the CLK0 and CLK1 bits in the
ADCON register that control the D0/CLKOUT pin. These
bits are only initialized to the default state when RESET is
performed using the RESET pin. After releasing from
RESET, self-calibration is performed, regardless of the
reset method or the state of the ACAL bit before RESET.
POWER-UP
All of the configuration registers are initialized to their
default state at power-up. A self-calibration is then
performed automatically. For the best performance, it is
strongly recommended to perform an additional
self-calibration by issuing the SELFCAL command after
the power supplies and voltage reference have had time
to settle to their final values.
相關PDF資料 |
PDF描述 |
|---|---|
| ADS1256IDBT | Very Low Noise, 24-Bit Analog-to-Digital Converter |
| ADS1255 | Very Low Noise, 24-Bit Analog-to-Digital Converter |
| ADS1256 | Very Low Noise, 24-Bit Analog-to-Digital Converter |
| ADS1271 | 24 BIT WIDE BANDWIDTH ANALOG TO DIGITAL CONVERTER |
| ADS1271IPW | 24 BIT WIDE BANDWIDTH ANALOG TO DIGITAL CONVERTER |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADS1256IDBRG4 | 功能描述:模數(shù)轉換器 - ADC 24Bit 30kSPS Very Lo-Noise Delta-Sigma RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1256IDBT | 功能描述:模數(shù)轉換器 - ADC 24Bit 30kSPS Very Lo-Noise Delta-Sigma RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1256IDBTG4 | 功能描述:模數(shù)轉換器 - ADC 24Bit 30kSPS Very Lo-Noise Delta-Sigma RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1257IRGWR | 功能描述:ANALOG TO DIGITAL CONVERTERS - A 制造商:texas instruments 系列:* 包裝:帶卷（TR） 零件狀態(tài):在售 封裝/外殼:20-VQFN 裸露焊盤 供應商器件封裝:20-VQFN（5x5） 標準包裝:3,000 |
| ADS1257IRGWT | 功能描述:24 Bit Analog to Digital Converter 2, 3 Input 1 Sigma-Delta 20-VQFN (5x5) 制造商:texas instruments 系列:- 包裝:剪切帶（CT） 零件狀態(tài):有效 位數(shù):24 采樣率（每秒）:30k 輸入數(shù):2，3 輸入類型:差分，單端 數(shù)據(jù)接口:SPI 配置:MUX-PGA-ADC 無線電 - S/H:ADC:- A/D 轉換器數(shù):1 架構:三角積分 參考類型:外部 電壓 - 電源，模擬:5V 電壓 - 電源，數(shù)字:1.8 V ~ 3.6 V 特性:PGA 工作溫度:-40°C ~ 105°C 封裝/外殼:20-VQFN 裸露焊盤 供應商器件封裝:20-VQFN（5x5） 標準包裝:1 |
發(fā)布緊急采購，3分鐘左右您將得到回復。