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ADN2817/ADN2818
Data Sheet
Rev. E | Page 14 of 40
I2C-INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION
1
A5
00000
X
MSB = 1 SET BY
PIN 19
0 = WR
1 = RD
SLAVE ADDRESS [6:0]
R/W
CTRL.
0
600
1-
00
7
Figure 18. Slave Address Configuration
S SLAVE ADDR, LSB = 0 (WR) A(S)
A(S)
DATA
SUB ADDR
A(S) P
DATA
060
01-
00
8
Figure 19. I2C Write Data Transfer
S
S = START BIT
P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
A(M) = LACK OF ACKNOWLEDGE BY MASTER
S
SLAVE ADDR, LSB = 0 (WR)
SLAVE ADDR, LSB = 1 (RD)
A(S)
SUB ADDR
A(S) DATA A(M)
DATA
P
A(M)
0
60
01
-0
09
Figure 20. I2C Read Data Transfer
START BIT
S
STOP BIT
P
ACK
WR
ACK
D0
D7
A0
A7
A5
A6
SLADDR[4:0]
SLAVE ADDRESS
SUB ADDRESS
DATA
SUB ADDR[6:1]
DATA[6:1]
SCK
SDA
06
001
-010
Figure 21. I2C Data Transfer Timing
tBUF
SDA
SS
P
S
SCK
tF
tLOW
tR
tF
tHD;STA
tHD;DAT
tSU;DAT
tHIGH
tSU;STA
tSU;STO
tHD;STA
tR
06
00
1-
01
1
Figure 22. I2C Port Timing Diagram