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| 型號： | ADN2817ACPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 1/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 32-LFCSP |
| 標準包裝： | 1,500 |
| 類型： | 時鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH |
| 輸入： | CML |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.7GHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 帶卷 (TR) |
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Continuous Rate 10 Mbps to 2.7 Gbps Clock
and Data Recovery ICs
Data Sheet
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
2007–2013 Analog Devices, Inc. All rights reserved.
FEATURES
Serial data input: 10 Mbps to 2.7 Gbps
Exceeds ITU-T jitter specifications
Integrated limiting amplifier
5 mV p-p sensitivity (ADN2817 only)
Adjustable slice level: ±100 mV (ADN2817 only)
Patented dual-loop clock recovery architecture
Programmable LOS detect (ADN2817 only)
Integrated PRBS generator and detector
No reference clock required
Loss of lock indicator
Supports double data rate
Bit error rate monitor (BERMON) or sample phase adjust options
Rate selectivity without the use of a reference clock
I2C interface to access optional features
Single-supply operation: 3.3 V
Low power
650 mW (ADN2817)
600 mW (ADN2818)
5 mm × 5 mm 32-lead LFCSP
APPLICATIONS
SONET OC-1, OC-3, OC-12, OC-48, and all associated FEC rates
Fibre Channel, 2× Fibre Channel, GbE, HDTV
WDM transponders
Regenerators/repeaters
Test equipment
GENERAL DESCRIPTION
The ADN2817/ADN2818 provide the receiver functions of
quantization, signal level detect, and clock and data recovery for
continuous data rates from 10 Mbps to 2.7 Gbps. The ADN2817/
ADN2818 automatically lock to all data rates without the need for
an external reference clock or programming. All SONET jitter
requirements are exceeded, including jitter transfer, jitter generation,
and jitter tolerance. All specifications are quoted for 40°C to
+85°C ambient temperature, unless otherwise noted.
This device, together with a PIN diode and a TIA preamplifier,
can implement a highly integrated, low cost, and low power
fiber optic receiver.
The ADN2817/ADN2818 have many optional features available
through an I2C interface. For example, the user can read back
the data rate onto which the ADN2817 or ADN2818 is locked,
or the user can set the device to lock only to one particular data
rate if provisioning of data rates is required. A BERMON circuit
provides an estimate of the received bit error rate (BER) without
interruption of the data. Alternatively, the user can adjust the
data sampling phase to optimize the received BER.
The ADN2817/ADN2818 are available in a compact 5 mm ×
5 mm, 32-lead, lead frame chip scale package.
FUNCTIONAL BLOCK DIAGRAM
LOOP
FILTER
PHASE
DET
SLICE
ADJUST
(ADN2817
ONLY)
LOS
DETECT
(ADN2817
ONLY)
DATA
RETIMING
I2C
REGISTERS
LOOP
FILTER
FREQ/
LOCK
DET
VCC VEE
ADN2817/ADN2818
CF1
CF2
LOL
REFCLKP/REFCLKN
(OPTIONAL)
SLICEP/
SLICEN
PIN
NIN
VREF
THRADJ
LOS
DATAOUTP/
DATAOUTN
CLKOUTP/
CLKOUTN
SCK
SDA
VCO
06001-
001
BERMON
VBER
BERMODE
PHASE
SHIFTER
ΔФ
Figure 1.
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