參數(shù)資料
型號(hào): ADE7754AR
廠商: ANALOG DEVICES INC
元件分類: 模擬信號(hào)調(diào)理
英文描述: ADE7754
中文描述: SPECIALTY ANALOG CIRCUIT, PDSO24
封裝: MS-013AD, SOIC-24
文件頁(yè)數(shù): 36/44頁(yè)
文件大?。?/td> 630K
代理商: ADE7754AR
REV. PrG 01/03
PRELIMINARY TECHNICAL DATA
ADE7754
36
Address
[A5:A0]
Default
Value
Name
R/W*
Length
Description
12h
ZXTOUT
R/W
16
FFFFh
Zero Cross Time Out register. If no zero crossing is detected
within a time period specified by this register the interrupt request
line (IRQ) will go active low for the corresponding line voltage.
The maximum time-out period is 2.3 seconds - see
Zero Crossing
Detection
.
Line Cycle register. The content of this register sets the
number of half line cycles while the active energy and the appar-
ent energy are accumulated in the LAENERGY and
LVAENERGY registers - See
Energy Calibration
.
Sag Line Cycle register. This register specifies the number of
consecutive half-line cycles where voltage channel input falls be-
low a threshold level. This register is common to the three line
voltage SAG detection. The detection threshold is specified by
SAGLVL register - See
Voltage SAG Detection
.
SAG Voltage Level. This register specifies the detection threshold
for SAG event. This register is common to the three line voltage
SAG detection. See the description of SAGCYC register for de-
tails.
Voltage Peak Level. This register sets the level of the voltage
peak detection. If the selected voltage phase exceeds this level, the
PKV flag in the status register is set - See
Table XII
.
Current Peak Level. This register sets the level of the current
peak detection. If the selected current phase exceeds this level, the
PKI flag in the status register is set - See
Table XII
.
PGA Gain register. This register is used to adjust the gain selec-
tion for the PGA in current and voltage channels - See
Analog
Inputs and Table X
. This register is also used to configuration of
the active energy accumulation - No-load threshold and sum of
absolute values.
Phase A Active Power Gain register. This register calculation can
be calibrated by writing to this register. The calibration range is
50% of the nominal full scale active power. The resolution of the
gain adjust is 0.0244% / LSB.
Phase B Active Power Gain
Phase C Active Power Gain
VA Gain register. This register calculation can be calibrated by
writing this register. The calibration range is 50% of the nominal
full scale real power. The resolution of the gain adjust is
0.02444% / LSB.
Phase B VA Gain
Phase C VA Gain
Phase A Phase Calibration Register
Phase B Phase Calibration Register
Phase C Phase Calibration Register
Phase A Power Offset Calibration Register
Phase B Power Offset Calibration Register
Phase C Power Offset Calibration Register
CF Scaling Numerator register. The content of this register is
used in the numerator of CF output scaling.
CF Scaling Denominator register. The content of this register
is
used in the denominator of CF output scaling.
Active Energy register divider
Apparent Energy register divider
Phase A Current channel RMS register. The register contains the
RMS component of one input of the current channel. The source
is selected by data bits in the mode register.
Phase B Current channel RMS register.
Phase C Current channel RMS register.
13h
LINCYC
R/W
16
FFFFh
14h
SAGCYC
R/W
8
FFh
15h
SAGLVL
R/W
8
0
16h
VPEAK
R/W
8
FFh
17h
IPEAK
R/W
8
FFh
18h
GAIN
R/W
8
0
19h
AWG
R/W
12
0
1Ah
1Bh
1Ch
BWG
CWG
AVAG
R/W
R/W
R/W
12
12
12
0
0
0
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
BVAG
CVAG
APHCAL
BPHCAL
CPHCAL
AAPOS
BAPOS
CAPOS
CFNUM
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
12
12
5
5
5
12
12
12
12
0
0
0
0
0
0
0
0
0h
26h
CFDEN
R/W
12
3Fh
27h
28h
29h
WDIV
VADIV
AIRMS
R/W
R/W
R
8
8
24
0
0
0
2Ah
2Bh
BIRMS
CIRMS
R
R
24
24
0
0
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