![](http://datasheet.mmic.net.cn/310000/ADE7754_datasheet_16240613/ADE7754_30.png)
REV. PrG 01/03
PRELIMINARY TECHNICAL DATA
ADE7754
–
30
–
The total apparent power calculated by the ADE7754 in the
Line accumulation mode depends on the configuration of the
VAMOD bits in the VAMode register. Each term of the
formula can be disabled or enabled by the LVASEL bits of
the VAMode register. The different configurations are de-
scribed in Table VI.
VA-
VASEL0
VASEL1
MOD
0d
V
Arms
x I
Arms
+ V
Brms
x I
Brms
1d
V
Arms
xI
Arms
+(V
Arms+
V
Crms
)/2xI
Brms
+ V
Crms
x I
Crms
2d
V
Arms
x I
Arms
+ V
Arms
x I
Brms
VASEL2
+ V
Crms
x I
Crms
+ V
Crms
x I
Crms
Table VI - Total Line Apparent Energy calculation
The Line Apparent Energy accumulation uses the same
signal path as the Apparent Energy accumulation. The LSB
size of these two registers is equivalent.
The ADE7754 accumulates the Total Reactive Power signal
in the LAENERGY register. This mode is selected by setting
to logic one bit5 of the WAVMode register (Add. 0Ch).
When this bit is set the accumulation of the Active Energy
over half line cycles in the LAENERGY register is disabled
and is done instead in the LVAENERGY register. In this
mode, the accumulation of the Apparent Energy over half line
cycles in the LVAENERGY is no-longer available - see
Figure 31. As the LVAENERGY register is an unsigned
value, the accumulation of the active energy in the
LVAENERGY register is unsigned. In this mode (reactive
energy), the selection of the phases accumulated in the
LAENERGY and LVAENERGY registers is done by the
LWATSEL selection bits of the WATMode register.
ENERGIES SCALING
The ADE7754 provides measurements of the Active, Reac-
tive and Apparent energies. These measurements do not have
the same scaling and cannot be compared directly to each
others.
When measuring the different energies with the ADE7754
with 50Hz signals at different power factor, the ratio between
the energies is:
PF=1
PF=0.707
Active
Wh
Wh x 0.707
Energy
Reactive
0
Wh x 0.707 / 9.546
Energy
Apparent
Wh / 3.657
Wh / 3.657
Energy
PF=0
0
Wh / 9.546
Wh / 3.657
CHECK SUM REGISTER
The ADE7754 has a check sum register (CHECKSUM[5:0])
to ensure the data bits received in the last serial read
operation are not corrupted. The 6-bit Checksum register is
reset before the first bit (MSB of the register to be read) is
put on the DOUT pin. During a serial read operation, when
each data bit becomes available on the rising edge of SCLK,
the bit will be added to the Checksum register. In the end of
the serial read operation, the content of the Checksum
register will equal to the sum of all ones in the register
previously read. Using the Checksum register, the user can
determine if an error has occurred during the last read
operation.
Note that a read to the Checksum register will also generate
a checksum of the Checksum register itself.
CONTENT OF REGISTER (n-bytes)
DOUT
Σ
CHECKSUM REGISTER ADDR: 3EH
Figure 38 - Checksum register for Serial Interface Read