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參數(shù)資料
| 型號(hào)： | ADE7169ASTZF16 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | Single-Phase Energy Measurement IC with 8052 MCU, RTC and LCD driver |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, QCC64 |
| 封裝： | 9 X 9 MM, ROHS COMPLIANT, MO-22-VMMD-4, LFCSP-64 |
| 文件頁(yè)數(shù)： | 41/140頁(yè) |
| 文件大?。?/td> | 1359K |
| 代理商： | ADE7169ASTZF16 |
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Preliminary Technical Data
ADE7169F16
Rev. PrD | Page 41 of 140
2
CYCEND
Logic one indicates the end of the energy accumulation over an integer number of half
line cycles.
Logic one indicates that no zero crossing on the line voltage happened for the last
ZXTOUT half line cycles.
Logic one indicates detection of a zero crossing in the voltage channel.
1
ZXTO
0
ZX
Table 38. Interrupt Enable Register 1 SFR (MIRQENL, 0xD9)
Bit
Location
7-6
Reserved
5
FAULTSIGN
Interrupt Flag
Description
Reserved.
When this bit is set, the FAULTSIGN bit set creates a pending ADE interrupt to the 8052
core.
When this bit is set, the VARSIGN bit set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the APSIGN bit set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the VANOLOAD bit set creates a pending ADE interrupt to the 8052
core.
When this bit is set, the RNOLOAD bit set creates a pending ADE interrupt to the 8052
core.
When this bit is set, the APNOLOAD bit set creates a pending ADE interrupt to the 8052
core.
4
3
2
VARSIGN
APSIGN
VANOLOAD
1
RNOLOAD
0
APNOLOAD
Table 39. Interrupt Enable Register 2 SFR (MIRQENM, 0xDA)
Bit
Location
7
CF2
6
CF1
5
VAEOF
4
REOF
3
AEOF
2
VAEHF
1
REHF
0
AEHF
Table 40. Interrupt Enable Register 3 SFR (MIRQENH, 0xDB)
Bit
Location
7-6
-
5
WFSM
4
PKI
3
PKV
2
CYCEND
1
ZXTO
0
ZX
Interrupt Flag
Description
When this bit is set, a CF2 pulse issued creates a pending ADE interrupt to the 8052 core.
When this bit is set, a CF1 pulse issued creates a pending ADE interrupt to the 8052 core.
When this bit is set, the VAEOF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the REOF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the AEOF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the VAEHF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the REHF flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the AEHF flag set creates a pending ADE interrupt to the 8052 core.
Interrupt Flag
Description
Reserved
When this bit is set, the WFSM flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the PKI flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the PKV flag set creates a pending ADE interrupt to the 8052 core..
When this bit is set, the CYCEND flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the ZXTO flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the ZX flag set creates a pending ADE interrupt to the 8052 core.
ANALOG INPUTS
The ADE7169F16 has two fully differential voltage input
channels. The maximum differential input voltage for input
pairs VP/VN and IP/IN are ±0.5 V. In addition, the maximum
signal level on analog inputs for VP/VN and IP/ IN is ±0.5 V
with respect to AGND.
Each analog input channel has a PGA (programmable gain
amplifier) with possible gain selections of 1, 2, 4, 8, and 16. The
gain selections are made by writing to the GAIN register in the
Energy Measurement Register List—see Table 33 and Figure 17.
Bits 0 to 2 select the gain for the PGA in the current channel, and
the gain selection for the PGA in voltage channel is made via
Bits 5 to 7. Figure 16 shows how a gain selection for the current
channel is made using the gain register.
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