參數(shù)資料
型號(hào)： ADE7169ASTZF16
廠商： ANALOG DEVICES INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： Single-Phase Energy Measurement IC with 8052 MCU, RTC and LCD driver
中文描述： SPECIALTY ANALOG CIRCUIT, QCC64
封裝： 9 X 9 MM, ROHS COMPLIANT, MO-22-VMMD-4, LFCSP-64
文件頁(yè)數(shù)： 27/140頁(yè)
文件大?。?/td> 1359K
代理商： ADE7169ASTZF16
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Preliminary Technical Data
ADE7169F16
Rev. PrD | Page 27 of 140
EPSR
ESAG
EBAT
EBSO
EVDCIN
FPSR
FSAG
FBAT
FBSO
FVDCIN
FPSM
IPSME Addr. 0ECh
IPSMF Addr. 0F8h
ETI
EPSM
ESI
PTI
PSI
IEIP2 Addr. 0A9h
ADEAUTOCLR
EPSR
FPSR
ESAG
FSAG
EBAT
FBAT
EVSW
FVSW
EBSO
FBSO
FPSM
Pending PSM interrupt
EPSM
TRUE
EVSW
reserved
reserved
reserved
reserved
EADE
: Not involved in PSM Interrupt signal chain
FVSW
EVDCIN
FVDCIN
Figure 10: PSM Interrupt Sources
Battery Switchover and Power Supply Restored
PSM Interrupt
The ADE7169F16 can be configured to generate a PSM
interrupt when the source of V
SW
changes from V
DD
to V
BAT
,
indicating battery switchover. Setting the EBSO bit in the
Power Management Interrupt Enable SFR (IPSME, 0xEC)
enables this event to generate a PSM interrupt.
The ADE7169F16 can also be configured to generate an
interrupt when the source of V
SW
changes from V
BAT
to V
DD
,
indicating that the V
DD
power supply has been restored. This
event is enabled to generate a PSM interrupt by setting the
EPSR bit in the Power Management Interrupt Enable SFR
(IPSME, 0xEC).
The flags in the Power Management Interrupt Flag SFR (IPSMF,
0xF8) for these interrupts, BSOF and PSRF are set regardless of
whether the respective enable bits have been set. The battery
switchover and power supply restore event flags, BSOF and
PSRF, are latched. These events must be cleared by writing a
zero to these bits. Bit 6 in the Peripheral Configuration SFR
(PERIPH, 0xF4), VSWSOURCE, tracks the source of V
SW
. The
bit is set when V
SW
is connected to V
DD
and cleared when V
SW
is
connected to V
BAT
.
V
SW
Monitor PSM Interrupt
The ADE7169F16 can be configured to generate a PSM
interrupt when V
SW
changes magnitude by more than a
configurable threshold. This threshold is set in the
Temperature and Supply Delta SFR (DIFFPROG, 0xF3) –see
Supply Voltage Measurement section. Setting the EVSW bit in
the Power Management Interrupt Enable SFR (IPSME, 0xEC)
enables this event to generate a PSM interrupt.
The V
SW
voltage is measured using a dedicated ADC. These
measurements take place in the background at intervals to
check the change in V
SW
. Conversions can also be initiated by
writing to the Start ADC Measurement SFR (ADCGO, 0xD8).
The EVSW flag will indicate that a V
SW
measurement is ready.
See the Supply Voltage Measurement section for details on how
V
SW
is measured.
V
BAT
Monitor PSM Interrupt
The V
BAT
voltage is measured using a dedicated ADC. These
measurements take place in the background at intervals to
check the change in V
BAT
. The BATTF bit is set when the battery
level is lower than the threshold set in the Battery detection
threshold SFR (BATVTH, 0xFA) or when a new measurement
is ready in the Battery ADC value SFR (BATADC, 0xDF) - see
Battery measurement section. Setting the EBATT bit in the
Power Management Interrupt Enable SFR (IPSME, 0xEC)
enables this event to generate a PSM interrupt.
V
DCIN
Monitor PSM Interrupt
The V
DCIN
voltage is monitored by a comparator. The FVDC bit
in the Power Management Interrupt Flag SFR (IPSMF, 0xF8) is
set when the V
DCIN
input level is lower than 1.2 V. Setting the
EVDCIN bit in the Power Management Interrupt Enable SFR
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