參數(shù)資料
型號： ADE7169ACPF16
廠商： ANALOG DEVICES INC
元件分類： 模擬信號調(diào)理
英文描述： Single-Phase Energy Measurement IC with 8052 MCU, RTC and LCD driver
中文描述： ANALOG CIRCUIT, QCC64
封裝： 9 X 9MM, MO-220VMMD, LFCSP-64
文件頁數(shù)： 109/140頁
文件大?。?/td> 1359K
代理商： ADE7169ACPF16
Preliminary Technical Data
ADE7169F16
PLL
The ADE7169F16 is intended for use with a 32.768 kHz watch crystal. A PLL locks onto a multiple of this frequency to provide a stable
4.096 MHz clock for the system. The core can operate at this frequency or at binary submultiples of it to allow power saving when
maximum core performance is not required. The default core clock is the PLL clock divided by 4 or 1.024 MHz. The ADE energy
measurement clock is derived from the PLL clock and is maintained at 4.096/5 MHz, 819.2 kHz across all CD settings. The PLL is
controlled by the CD[2:0] bits in the Power Control SFR (POWCON, 0xC5). To protect erroneous changes to the Power Control SFR
(POWCON, 0xC5), a key is required to modify the register. First the POWCON Key SFR (KYREG, 0xC1) is written with the key, 0xA7,
and then a new value is written to the Power Control SFR (POWCON, 0xC5).
Rev. PrD | Page 109 of 140
If the PLL loses lock, the MCU is reset and the PLLFAULT bit is set in the Peripheral Configuration SFR (PERIPH, 0xF4). Set the
PLL_FLT_ACK bit in the Start ADC Measurement SFR (ADCGO, 0xD8) to acknowledge the PLL fault, clearing the PLLFAULT flag.
PLL SFR REGISTER LIST
Power Control SFR (POWCON, 0xC5)
Bit
Location
Mnemonic
7-5
RESERVED
Bit
Default
Value
0
Description
4
COREOFF
0
Set this bit to shut down the core if in the PSM1 operating mode.
3
2-0
RESERVED
CD[2:0]
010
Controls the core clock frequency, F
core
. F
core
=4.096MHz/2
CD
CD[2:0]
F
core
(MHz)
0
0
0
4.096
0
0
1
2.048
0
1
0
1.024
0
1
1
0.512
1
0
0
0.256
1
0
1
0.128
1
1
0
0.064
1
1
1
0.032
Table 106. POWCON Key SFR (KYREG, 0xC1)
Bit
Location
Mnemonic
7-0
KYREG
Bit
Default
Value
Description
0
Write 0xA7 to the KYREG SFR before writing the POWCON SFR, to unlock it.
Peripheral Configuration SFR (PERIPH, 0xF4)
Bit
Location
Mnemonic
7
RXFLAG
6
VSWSOURCE
Bit
Default
Value
0
1
Description
If set, indicates that VDD power supply is ok for operation
If set, indicates that a RX Edge event triggered wakeup from PSM2
Indicates the power supply that is connected internally to V
SW
.
0 V
SW
=V
BAT
1 V
SW
=V
DD
5
VDD_OK
0
4
PLL_FLT
0
If set, indicates that PLL is not locked
3
RESERVED
2
EXTREFEN
0
Set this bit if an external reference is connected to the REFIN pin.
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