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| 型號： | ADE7169ACPF16-RL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Single-Phase Energy Measurement IC with 8052 MCU, RTC and LCD driver |
| 中文描述： | ANALOG CIRCUIT, QCC64 |
| 封裝： | 9 X 9MM, MO-220VMMD, LFCSP-64 |
| 文件頁數(shù)： | 130/140頁 |
| 文件大小： | 1359K |
| 代理商： | ADE7169ACPF16-RL |
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ADE7169F16
Preliminary Technical Data
Rev. PrD | Page 130 of 140
00
01
10
11
Configures the length of the I2C received FIFO buffer. The I2C peripheral
will stop when I2CRCT[4:0] + 1 bytes have been read or if an error has
occured
F
core
/ 16 = 256kHz if F
core
= 4.096MHz
F
core
/ 32 = 128kHz if F
core
= 4.096MHz
F
core
/ 64 = 624Hz if F
core
= 4.096MHz
F
core
/ 128= 32kHz if F
core
= 4.096MHz
4-0
0xEC –
oxE8
I2CRCT[4:0]
0
Table 130. I2C Slave Address SFR (I2CADR, 0xE9)
Bit
Location
Mnemonic
7-1
I2CSLVADR
Bit
Default
Value
Description
0
Address of the I2C slave being adressed
Writing to this register start the I2C transmission (Read or write)
Command bit for Read or Write
When this bit is set to logic one, a read command will be transmitted on
the I2C bus. Data from slave in SPI2CRx SFR is expected after command
byte
When this bit is set to logic zero, a write command will be transmitted on
the I2C bus. Data to slave is expected in SPI2CTx SFR
0
I2CR_W
0
Table 131. I2C Interrupt Status Register SFR (I2CSTAT, 0xEA)
Bit
Location
Mnemonic
7
I2CBUSY
Bit
Default
Value
Description
0
This bit is set to logic one when the I2C interface is used. When set, the Tx
FIFO is emptied
I2C no acknlowledgement transmit interrupt
This bit is set to logic one when the slave device did not send an
acknlowledgement. The I2C communication is stopped after this event.
Erased by clearing bit.
I2C receive interrupt
This bit is set to logic one when the receive FIFO is not empty
This bit is cleared to logic zero by reading the SPI2CRx SFR and the FIFO is
empty
I2C transmit interrupt
This bit is set to logic one when the transmit FIFO is empty
This bit is cleared to logic zero by writing to the SPI2CTx SFR
Status bit for 3 or 4 bytes deep I2C FIFO. The FIFO monitored in these 2
bits is the one currently used in I2C communication (Receive or Transmit)
as only one of them is active at a time
[1:0]
00
FIFO empty
01
Reserved
10
FIFO Half full
11
FIFO Full
Set when trying to write and read at the same time
Set when write was attempted when I2C transmit FIFO was full
6
I2CNOACK
0
5
I2CRxIRQ
0
4
I2CTxIRQ
0
3-2
I2CFIFOSTAT[1:0]
0
1
0
I2CACC_ERR
I2CTxWR_ERR
0
0
An I2C interrupt occurs
*
Purchase of licensed I
2
C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I
2
C
Patent Rights to use the ADE7XXX in an I
2
C system, provided that the system conforms to the I
2
C Standard Specification as defined by Philips.
READ AND WRITE OPERATIONS
Figure 85 and Figure 86 depict I2C read and write operations, respectively. Note that the LSB of the I2CADR register is used to select
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