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參數(shù)資料
| 型號： | ADE7169ACPF16-RL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Single-Phase Energy Measurement IC with 8052 MCU, RTC and LCD driver |
| 中文描述： | ANALOG CIRCUIT, QCC64 |
| 封裝： | 9 X 9MM, MO-220VMMD, LFCSP-64 |
| 文件頁數(shù)： | 121/140頁 |
| 文件大?。?/td> | 1359K |
| 代理商： | ADE7169ACPF16-RL |
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Preliminary Technical Data
ADE7169F16
possible.
Rev. PrD | Page 121 of 140
Modes 1 and 3 Baud Rate
=
16
1
×
Timer 2 Overflow Rate
Therefore, when Timer 2 is used to generate baud rates, the
timer increments every two clock cycles rather than every core
machine cycle as before. It increments six times faster than
Timer 1, and, therefore, baud rates six times faster are possible.
Because Timer 2 has 16-bit autoreload capability, very low baud
rates are still possible.
Timer 2 is selected as the baud rate generator by setting the
TCLK and/or RCLK in T2CON. The baud rates for transmit
and receive can be simultaneously different. Setting RCLK
and/or TCLK puts Timer 2 into its baud rate generator mode as
shown in Figure 78.
In this case, the baud rate is given by the formula
Modes 1 and 3 Baud Rate
=
(
)
[
]
(
)
L
RCAP
H
RCAP
F
core
2
:
2
65536
16
×
F
CORE
T2
PIN
TR2
CONTROL
TL2
(8 BITS)
TH2
(8 BITS)
RELOAD
EXEN2
CONTROL
T2EX
PIN
TRANSITION
DETECTOR
EXF 2
TIMER 2
INTERRUPT
NOTE: AVAILABILITY OF ADDITIONAL
EXTERNAL INTERRUPT
RCAP2L
RCAP2H
TIMER 2
OVERFLOW
2
16
16
RCLK
TCLK
RX
CLOCK
TX
CLOCK
0
0
1
1
1
0
SMOD
TIMER 1
OVERFLOW
C/T2 = 0
C/T2 = 1
0
Figure 78. Timer 2, UART Baud Rates
UART Timer Generated Baud Rates
The high integer dividers in a UART block mean that high
speed baud rates are not always possible. Also, generating baud
rates requires the exclusive use of a timer, rendering it unusable
for other applications when the UART is required. To address
this problem, the ADE7169F16 has a dedicated baud rate timer
(UART Timer) specifically for generating highly accurate baud
rates. UART Timer can be used instead of Timer 1 or Timer 2
for generating very accurate high speed UART baud rates
including 115200. UART Timer also allows a much wider range
of baud rates to be obtained. In fact, every desired bit rate from
12 bps to 393216 bps can be generated to within an error of
±0.8%. UART Timer also frees up the other three timers,
allowing them to be used for different applications. A block
diagram of UART Timer is shown in Figure 79.
(1 + SBAUDF/64)
UART Timer
Rx/Tx CLOCK
F
CORE
UARTBAUDEN
Rx CLOCK
Tx CLOCK
TIMER 1/TIMER 2
Rx CLOCK
FRACTIONAL
DIVIDER
0
0
1
1
TIMER 1/TIMER 2
Tx CLOCK
32
2
D IV+SBTH
Figure 79. UART Timer, UART Baud Rate
Two SFRs Enhanced Serial baud rate control SFR (SBAUDT,
0x9E) and UART Timer Fractional Divider SFR (SBAUDF,
0x9D) are used to control UART Timer. SBAUDT is the baud
rate control SFR; it sets up the integer divider (DIV) and the
extended divider (SBTH) for UART Timer.
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