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參數(shù)資料
| 型號： | ADDI7100BCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR CCD SIGNAL7 32LFCSP |
| 標準包裝： | 5,000 |
| 類型： | CCD 信號處理器，12 位 |
| 應(yīng)用： | 數(shù)碼相機 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 帶卷 (TR) |
ADDI7100
Rev. C | Page 14 of 20
APPLICATIONS INFORMATION
The ADDI7100 is a complete analog front-end (AFE) product
for digital still camera and camcorder applications. As shown in
Figure 14, the CCD image (pixel) data is buffered and sent to
the ADDI7100 analog input through a series input capacitor.
The ADDI7100 performs the dc restoration, CDS sampling,
gain adjustment, black level correction, and analog-to-digital
conversion. The digital output data of the ADDI7100 is then
processed by the image processing ASIC. The internal registers
of the ADDI7100—used to control gain, offset level, and other
functions—are programmed by the ASIC or by a microprocessor
through a 3-wire serial digital interface. A system timing generator
provides the clock signals for both the CCD and the AFE (see
0.1F
07
60
8-
01
4
CCD
CCDIN
BUFFER
VOUT
ADDI7100
ADCOUT
REGISTER
DATA
SERIAL
INTERFACE
DIGITAL
OUTPUTS
DIGITAL IMAGE
PROCESSING
ASIC
TIMING
GENERATOR
V-DRIVER
CCD
TIMING
CDS/CLAMP
TIMING
Figure 14. System Applications Diagram
24
REFB
23
REFT
22
CCDIN
21 AVSS
D2
1
D3
2
D0
D1
D4
3
20 AVDD
19
SHD
18
SHP
17
CLPOB
D5
4
D6
5
D7
6
D8
7
D9
8
DATA
OUTPUTS
12
D1
0
D1
1
910
3V
DRIVER
SUPPLY
3V
ANALOG
SUPPLY
3V
ANALOG
SUPPLY
DR
V
D
R
VSS
DV
DD
DV
S
PB
L
K
12 13 14 15 16
5
CLOCK
INPUTS
3
SERIAL
INTERFACE
CCDIN
ADDI7100
TOP VIEW
(Not to Scale)
1.0F
0.1F
NC = NO CONNECT (NOT INTERNALLY CONNECTED, MAY BE TIED TO GROUND OR LEFT FLOATING).
PIN 1
IDENTIFIER
32 31 30 29 28 27 26 25
NC
VD
SC
K
SDA
TA
SL
11
DA
TA
C
L
K
07
60
8-
0
15
VD OUTPUT FROM ASIC/DSP
(SHOULD BE GROUNDED IF NOT USED.)
Figure 15. Recommended Circuit Configuration for CCD Mode
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