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| 型號： | ADAV803ASTZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | 8-Channel 14-Bit Single-Supply Voltage-Output DAC; Package: LQFP (10x10mm); No of Pins: 52; Temperature Range: Industrial |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | ROHS COMPLIANT, MS-026BCD, LQFP-64 |
| 文件頁數(shù)： | 36/56頁 |
| 文件大?。?/td> | 906K |
| 代理商： | ADAV803ASTZ |
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ADAV803
Table 26. Receiver Buffer Configuration Register
RES
7
ADDRESS = 0001011 (0x0B)
RxBCONF5
If the user bits are formatted according to the IEC60958-3 standard and the DAT category is detected, the user bit
enabled only when there is a change in the start (ID) bit.
interrupt is
0 = User bit interrupt is enabled in normal mode.
If the DAT category is detected, the user bit interrupt is enabled only if there is a change in the start (ID) bit.
termines whether Channel A and Channel B user bits are stored in the buffer together or separated
and B.
between A
0 = User bits are stored together.
1 = User bits are stored separately.
RxBCONF3
Defines the function of RxCSBINT.
0 = RxCSBINT are set when a new block of r
1 = RxCSBINT is set only if the first five bytes
status block.
RxBCONF2–1
Defines the user bit buffer.
e ignored.
00 = User bits ar
10 = Formats the received user bits according to Byte 1, Bit 4 to Bit 7, of the channel status, if the PRO bit is set. If the
PRO bit is not set, formats the user bits according to the
11 = Reserved.
R
0 = 384 bits with Preamble Z as the sta
8 b
h Pr
st
1 = 76
its wit
eamble Z as the
rt of the buffer.
Rev. 0 | Page 36 of 56
RES
6
F5
RxBCONF4
4
NF3
RxB
2, 1
RxBCONF0
0
RxBCON
5
RxBCO
3
CONF2–1
eceiver channel status is read, which is 192 audio frames.
of the receiver channel status block changes from the previous channel
IEC60958-3 standard.
xBCONF0
Defines the user bit buffer size, if RxBCONF2–1 = 01.
rt of the buffer.
a
RxBCONF4
1 =
This bit de
01 = Updates the second user bit buffer when the first user bit buffer is full.
Table 27. Transmitter Control Register
ADDRESS = 0001100 (0x0C)
TxVALIDITY
TxRATIO2–0
TxCLKSEL1–0
TxENABLE
RES
7
TxVALIDITY
6
TxRATIO2–0
5, 4, 3
TxCLKSEL1–0
2, 1
TxENABLE
0
This bit is used to set or clear the VALIDITY bit in the AES3/SPDIF transmit stream.
0 = Audio is suitable for D/A conversion.
1 = Audio is not suitable for D/A conversion.
Determines the AES3/SPDIF transmitter to AES3/SPDIF receiver ratio.
000 = Transmitter to receiver ratio is 1:1.
001 = Transmitter to receiver ratio is 1:2.
010 = Transmitter to receiver ratio is 1:4.
101 = Transmitter to receiver ratio is 2:1.
110 = Transmitter to receiver ratio is 4:1.
Selects the clock source for the AES3/SPDIF transmitter.
ock source for the transmitter.
00 = Internal Clock 1 is the cl
01 = Internal Clock 2 is the clock source for the transmitter.
10 = Recovered PLL clock is the clock sour
11 = Reserved.
Enables the AES3/SPDIF transmitter.
0 = AES
1 = AES3/SPDIF transmitter is enabled.
ce for the transmitter.
3/SPDIF transmitter is disabled.
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| ADAV803ASTZ-REEL | 功能描述:IC CODEC AUDIO R-DVD 3.3V 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標準包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標準 ADC / DAC (db):81.5 / 88 動態(tài)范圍，標準 ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
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