- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375252 > ADAU1701 (Analog Devices, Inc.) SigmaDSP 28/56-Bit Audio Processor with 2ADC/4DAC PDF資料下載
參數(shù)資料
| 型號(hào)： | ADAU1701 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | SigmaDSP 28/56-Bit Audio Processor with 2ADC/4DAC |
| 中文描述： | SigmaDSP的28/56-Bit音頻處理器2ADC/4DAC |
| 文件頁數(shù)： | 34/43頁 |
| 文件大?。?/td> | 625K |
| 代理商： | ADAU1701 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁當(dāng)前第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁
ADAU1701
Preliminary Technical Data
Table 46. Serial Output Control Register (2078)
Register Bits
Function
15:14
Unused
13
OUTPUT_LRCLK Polarity
0 = Frame Begins on Falling Edge
1 = Frame Begins on Rising Edge
12
OUTPUT_BCLK Polarity
0 = Data Changes on Falling Edge
1 = Data Changes on Rising Edge
11
Master/Slave
0 = Slave
1 = Master
10:9
OUTPUT_BCLK Frequency (Master Mode only)
00 = core_clock/16
01 = core_clock/8
10 = core_clock/4
11 = core_clock/2
8:7
OUTPUT_LRCLK (Master Mode only)
00 = core_clock/1024
01 = core_clock/512
10 = core_clock/256
6
Frame Sync Type
0 = LRCLK
1 = Pulse
5
Serial Output/TDM Mode Control
0 = 8 Serial Data Outputs
1 = Enable TDM on SDATA_OUTx
4:2
MSB Position
000 = Delay by 1
001 = Delay by 0
010 = Delay by 8
011 = Delay by 12
100 = Delay by 16
101 Reserved
111 Reserved
1:0
Output Word Length
00 = 24 Bits
01 = 20 Bits
10 = 16 Bits
11 = Reserved
Rev. PrF | Page 34 of 43
SERIAL OUTPUT CONTROL REGISTERS
OUTPUT_LRCLK Polarity (Bit 13)
When set to 0, the left channel data is clocked when
OUTPUT_LRCLK is low, and the right channel data clocked
when OUTPUT_LRCLK is high. When set to 1, the right
channel data is clocked when OUTPUT_LRCLK is low, and the
left channel data clocked when OUTPUT_LRCLK is high.
OUTPUT_BCLK Polarity (Bit 12)
This bit controls on which edge of the bit clock the output data
is clocked. Data changes on the falling edge of OUTPUT_BCLK
when this bit is set to 0, and on the rising edge when this bit is
set at 1.
Master/Slave (Bit 11)
This bit sets whether the output port is a clock master or slave.
The default setting is slave; on power-up, Pins OUTPUT_BCLK
and OUTPUT_LRCLK are set as inputs until this bit is set to 1,
at which time they become clock outputs.
OUTPUT_BCLK Frequency (Bits 10:9)
When the output port is being used as a clock master, these bits
set the frequency of the output bit clock, which is divided down
from the internal 49.152 MHz core clock.
OUTPUT_LRCLK Frequency (Bits 8:7)
When the output port is used as a clock master, these bits set
the frequency of the output word clock on the
OUTPUT_LRCLK pins, which is divided down from the
internal 49.152 MHz
core clock.
Frame Sync Type (Bit 6)
This bit sets the type of signal on the OUTPUT_LRCLK pins.
When set to 0, the signal is a word clock with a 50% duty cycle;
when set to 1, the signal is a pulse with a duration of one bit
clock at the beginning of the data frame.
Serial Output/TDM Mode Control (Bit 5)
Setting this bit to 1 changes the output port from multiple serial
outputs to a single TDM output stream on the appropriate
SDATA_OUTx pin. This bit must be set in both serial output
control registers to enable 16-channel TDM on SDATA_OUT0.
MSB Position (Bits 4:2)
These three bits set the position of the MSB of data with respect
to the LRCLK edge. The data output of the ADAU1701 is always
MSB first.
Output Word Length (Bits 1:0)
These bits set the word length of the output data-word. All bits
following the LSB are set to 0.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADAU1701JSTZ | SigmaDSP 28/56-Bit Audio Processor with 2ADC/4DAC |
| ADAU1701JSTZ-RL | SigmaDSP 28/56-Bit Audio Processor with 2ADC/4DAC |
| ADAV400 | Audio Codec with Embedded SigmaDSP Processor |
| ADAV400KSTZ | Audio Codec with Embedded SigmaDSP Processor |
| ADAV400KSTZ-REEL | Audio Codec with Embedded SigmaDSP Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADAU1701JSTZ | 功能描述:IC AUDIO PROC 2ADC/4DAC 48-LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
| ADAU1701JSTZ-RL | 功能描述:IC AUDIO PROC 2ADC/4DAC 48-LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
| ADAU1701MINIBZ | 制造商:Analog Devices 功能描述:EVAL BD SIGMADSPMULTICHANAUDIO PROCESSOR - Bulk |
| ADAU1702 | 制造商:AD 制造商全稱:Analog Devices 功能描述:SigmaDSP 28-56-Bit Audio Processor with Two ADCs and Four DACs |
| ADAU1702JSTZ | 功能描述:IC AUDIO PROC 2ADC/4DAC 48-LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。