參數(shù)資料
型號： ADAU1701
廠商： Analog Devices, Inc.
英文描述： SigmaDSP 28/56-Bit Audio Processor with 2ADC/4DAC
中文描述： SigmaDSP的28/56-Bit音頻處理器2ADC/4DAC
文件頁數(shù)： 26/43頁
文件大?。?/td> 625K
代理商： ADAU1701
ADAU1701
Preliminary Technical Data
RAMS AND REGISTERS
Table 21. Control Port Addresses
SPI/ I
2
C Subaddress
0–1023 (0x0000–0x03FF)
1024–2047 (0x0400-0x07FF)
2048-2055 (0x0800-0x0807)
2056 (0x0808)
2057-2060 (0x0809-0x080C)
2064–2068 (0x080D-0x0814)
2069–2073 (0x0815-0x0819)
2074-2075 (0x081A-0x081B)
2076 (0x081C)
2077 (0x081D)
2078 (0x081E)
2079 (0x081F)
2080-2081 (0x0820-0x0821)
2082 (0x0822)
2083 (0x0823)
2084 (0x0824)
2085 (0x0825)
2086 (0x0826)
Table 22. RAM Read/Write Modes
Memory
Parameter RAM
Program RAM
1
Internal registers should be cleared first to avoid clicks/pops.
CONTROL PORT ADDRESSING
Table 21 shows the addressing of the ADAU1701’s RAM and
register spaces. The address space encompasses a set of registers
and two RAMs: one each for holding signal processing
parameters and holding the program instructions. The program
and parameter RAMs are initialized on power-up from on-
board boot ROMs (see Power-Up Sequence section).
Rev. PrF | Page 26 of 43
Register/RAM Name
Parameter RAM
Program RAM
Interface Registers 0 - 7
GPIO Pin Setting Register
Aux ADC Data Registers
Safeload Data Registers 0 – 4
Safeload Address Registers 0 - 4
Data Capture Registers 0–1
DSP Core Control Register
Reserved – do not write
Serial Output Control Register
Serial Input Control Register
Multi-Purpose Pin Configuration Registers 0 – 1
Auxiliary ADC & Power Control Register
Reserved – do not write
Auxiliary ADC Enable Register
Reserved – do not write
Oscillator Power-down Register
Read/Write Word Length
Write: 4 Bytes, Read: 4 Bytes
Write: 5 Bytes, Read: 5 Bytes
Read: 4 bytes, Write: 4 bytes
Read: 2 bytes, Write: 2 bytes
Read: 2 bytes, Write: 1 byte
Write: 5 Bytes, Read: N/A
Write: 2 Bytes, Read: N/A
Write: 2 Bytes, Read: 3 Bytes
Write: 2 Bytes, Read: 2 Bytes
Write: 1 Byte, Read: 1 Byte
Write: 2 Bytes, Read: 2 Bytes
Write: 1 Byte, Read: 1 Byte
Write: 3 Bytes, Read: 3 Bytes
Write: 2 Bytes, Read: 2 Bytes
Write: 2 Bytes, Read: 2 Bytes
Write: 2 Bytes, Read: 2 Bytes
Write: 2 Bytes, Read: 2 Bytes
Write: 2 Bytes, Read: 2 Bytes
Size
1024 × 28
1024 × 40
Address Range
0–1023
1024–2047
Read
Yes
Yes
Write
Yes
Yes
Write Modes
Direct Write
1
, Safeload Write
Direct Write
1
Table 22 shows the sizes and available writing modes of the
parameter and program RAMs.
All RAMs and registers have a default value of all zeros, except
for the program RAM which is loaded with the default program
as described in the Initialization section.
PARAMETER RAM
The parameter RAM is 28 bits wide and occupies Addresses 0 to
1023. The parameter RAM is initialized to all zeros on power-
up. The data format of the parameter RAM is twos complement
5.23. This means that the coefficients may range from +16.0
(minus 1 LSB) to –16.0, with 1.0 represented by the binary word
0000 1000 0000 0000 0000 0000 0000 or hexadecimal word
0x00 0x80 0x00 0x00.
The parameter RAM can be written and read using one of the
two following methods.
Direct Read/Write
This method allows direct access to the program and parameter
RAMs. This mode of operation is normally used during a
complete new load of the RAMs, using burst-mode addressing.
The clear registers bit in the core control register should be set
to 0 using this mode to avoid any clicks or pops in the outputs.
Note that it is also possible to use this mode during live
program execution, but since there is no handshaking between
the core and the control port, the parameter RAM will be
unavailable to the DSP core during control writes, resulting in
clicks and pops in the audio stream.
Safeload Write
Up to five safeload registers can be loaded with parameter RAM
address/data. The data is then transferred to the requested
address when the RAM is not busy. This method can be used
for dynamic updates while live program material is playing
through the ADAU1701. For example, a complete update of one
biquad section can occur in one audio frame, while the RAM is
not busy. This method is not available for writing to the
program RAM or control registers.
相關(guān)PDF資料
PDF描述
ADAU1701JSTZ SigmaDSP 28/56-Bit Audio Processor with 2ADC/4DAC
ADAU1701JSTZ-RL SigmaDSP 28/56-Bit Audio Processor with 2ADC/4DAC
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADAU1701JSTZ 功能描述:IC AUDIO PROC 2ADC/4DAC 48-LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
ADAU1701JSTZ-RL 功能描述:IC AUDIO PROC 2ADC/4DAC 48-LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
ADAU1701MINIBZ 制造商:Analog Devices 功能描述:EVAL BD SIGMADSPMULTICHANAUDIO PROCESSOR - Bulk
ADAU1702 制造商:AD 制造商全稱:Analog Devices 功能描述:SigmaDSP 28-56-Bit Audio Processor with Two ADCs and Four DACs
ADAU1702JSTZ 功能描述:IC AUDIO PROC 2ADC/4DAC 48-LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
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