參數(shù)資料
型號： ADAU1442YSVZ-3A
廠商： Analog Devices Inc
文件頁數(shù)： 6/93頁
文件大?。?/td> 0K
描述： IC SIGMADSP 28B 175MHZ 100TQFP
標準包裝： 1
系列： SigmaDSP®
類型： 音頻處理器
應用： 車載音頻
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應商設備封裝： 100-TQFP-EP（14x14）
包裝： 托盤
Data Sheet
ADAU1442/ADAU1445/ADAU1446
Rev. D | Page 13 of 92
Pin No.
Mnemonic
Type1
Description
6
BCLK2
D_IO
Bit Clock, Input Clock Domain 2. This pin is bidirectional, with the direction depending on whether
the Input Clock Domain 2 is set up as a master or slave. When not used, this pin can be left disconnected.
7
LRCLK2
D_IO
Frame Clock, Input Clock Domain 2. This pin is bidirectional, with the direction depending on whether
the Input Clock Domain 2 is set up as a master or slave. When not used, this pin can be left disconnected.
8
SDATA_IN1
D_IN
Serial Data Port 1 Input. When not used, this pin can be left disconnected.
9
BCLK1
D_IO
Bit Clock, Input Clock Domain 1. This pin is bidirectional, with the direction depending on whether
the Input Clock Domain 1 is set up as a master or slave. When not used, this pin can be left disconnected.
10
LRCLK1
D_IO
Frame Clock, Input Clock Domain 1. This pin is bidirectional, with the direction depending on whether
the Input Clock Domain 1 is set up as a master or slave. When not used, this pin can be left disconnected.
11
SDATA_IN0
D_IN
Serial Data Port 0 Input. When not used, this pin can be left disconnected.
12
BCLK0
D_IO
Bit Clock, Input Clock Domain 0. This pin is bidirectional, with the direction depending on whether
the Input Clock Domain 0 is set up as a master or slave. When not used, this pin can be left disconnected.
15
LRCLK0
D_IO
Frame Clock, Input Clock Domain 0. This pin is bidirectional, with the direction depending on whether
the Input Clock Domain 0 is set up as a master or slave. When not used, this pin can be left disconnected.
16
MP11
D_IO
Multipurpose, General-Purpose Input/Output. When not used, this pin can be left disconnected.
17
MP10
D_IO
Multipurpose, General-Purpose Input/Output. When not used, this pin can be left disconnected.
18
MP9
D_IO
Multipurpose, General-Purpose Input/Output. When not used, this pin can be left disconnected.
19
MP8
D_IO
Multipurpose, General-Purpose Input/Output. When not used, this pin can be left disconnected.
20
ADDR0
D_IN
Address 0 for I2C and SPI. In I2C mode, this pin, in combination with ADDR1, allows up to four
ADAU1442/ADAU1445/ADAU1446 devices to be used on the same I2C bus. In SPI mode, setting
ADDR0 either low or high allows up to two ICs to be used with a common SPI latch signal.
21
CLATCH
D_IN
SPI Latch Signal. Must go low at the beginning of an SPI transaction and high at the end of a
transaction. Each SPI transaction may take a different number of CCLK cycles to complete,
depending on the address and read/write bits that are sent at the beginning of the SPI transaction.
When not used, this pin should be tied to ground, preferably with a 10 k pull-down resistor.
22
SCL/CCLK
D_IN
Serial Clock/Continuous Clock. In I2C mode, this pin functions as SCL and is always an open collector
input, except when in self-boot mode, where it is an open collector output (I2C master). The line
connected to this pin should have a 2.0 k pull-up resistor. In SPI mode, this pin functions as CCLK
and is an input pin that can be either run continuously or gated off between SPI transactions.
23
SDA/COUT
D_IO
Serial Data/Continuous Output. In I2C mode, this pin functions as SDA and is a bidirectional open
collector. The line connected to the SDA pin should have a 2.0 k pull-up resistor. In SPI mode, this
pin functions as COUT and is used for reading back registers and memory locations. The COUT pin
is three-stated when an SPI read is not active.
24
ADDR1/CDATA
D_IN
Address 1/Continuous Data. In I2C mode, this pin functions as ADDR1 and, in combination with
ADDR0, sets the I2C address of the IC. This allows up to four ADAU1442/ADAU1445/ADAU1446
devices to be used on the same I2C bus. In SPI mode, this pin functions as CDATA and is the SPI
data input.
25, 37,
50, 75,
87, 100
DVDD
PWR
1.8 V Digital Supply. This can be supplied externally or generated from a 3.3 V supply with the
on-board 1.8 V regulator. Each DVDD pin should be decoupled to DGND with a 100 nF capacitor.
28
SELFBOOT
D_IN
Self-Boot Select. Allows the ADAU1442/ADAU1445/ADAU1446 to be controlled by the control port
or to perform a self-boot. Setting this pin high (that is, to 1) initiates a self-boot operation when the
ADAU1442/ADAU1445/ADAU1446 are brought out of a reset. This pin can be tied directly to a
voltage source or ground or pulled up/down with a resistor.
29
CLKMODE1
D_IN
Output Clock Mode 1. With CLKMODE0, this pin sets the frequency of the CLKOUT signal.
30
CLKMODE0
D_IN
Output Clock Mode 0. With CLKMODE1, this pin sets the frequency of the CLKOUT signal.
31
RSVD
D_IN
Reserved. Tie this pin to ground, preferably with a 10 k pull-down resistor.
32
PLL2
D_IN
PLL Mode Select Pin 2.
33
MP7
D_IO
Multipurpose, General-Purpose Input/Output. When not used, this pin can be left disconnected.
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