參數(shù)資料
型號(hào)： ADAU1442YSVZ-3A
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 47/93頁(yè)
文件大小： 0K
描述： IC SIGMADSP 28B 175MHZ 100TQFP
標(biāo)準(zhǔn)包裝： 1
系列： SigmaDSP®
類型： 音頻處理器
應(yīng)用： 車(chē)載音頻
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 托盤(pán)
ADAU1442/ADAU1445/ADAU1446
Data Sheet
Rev. D | Page 50 of 92
Sample Rate Conversion Before the DSP
If asynchronous input signals are present in the system, they
must be routed through the ASRC before being processed by
the DSP. This is made possible by routing the asynchronous
signals through the input side of the routing matrix to the
ASRC inputs. This is illustrated in Figure 43.
In such a situation, the ASRC target sample rate should be set
synchronous to the DSP. After conversion, the signals are
passed to the DSP and are then available in SigmaStudio in the
ASRC input cell.
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
16, 17
18, 19
20, 21
22, 23
FROM SERIAL
INPUT PORTS
FROM
S/PDIF Rx
STEREO
ASRCs
(8 × 2 CH)
RATE
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
8
TO DSP
07
69
6-
04
4
FARM
Figure 43. Routing Asynchronous Input Signals to DSP Inputs
Sample Rate Conversion After the DSP
After processing signals in the DSP, it is sometimes desirable to
output them asynchronous to the DSP rate, for example, when
an asynchronous external DAC is in the system. This can be
accomplished by routing the signals through the input side of
the routing matrix from the DSP-to-ASRC pairs to the ASRC
inputs. This is illustrated in Figure 44.
In this situation, the ASRC target sample rate can be set to any
desired value, and the audio data is sent to the output side of the
routing matrix.
TO FARM
(OUTPUT SIDE)
FROM DSP
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
16, 17
18, 19
20, 21
22, 23
FROM SERIAL
INPUT PORTS
STEREO
ASRCs
(8 × 2 CH)
RATE
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
8
0
7696
-0
45
FARM
Figure 44. Routing DSP Outputs to Asynchronous Output Signals
DSP Inputs and Outputs
In the DSP, the signals are represented as input and output blocks
within the SigmaStudio development tool and then undergo
processing as determined by the SigmaStudio schematic. There
are 21 input and output channel pairs, as shown in Figure 45. In
SigmaStudio, each pair is accessible as individual channels and,
therefore, does not need to remain as a pair.
FROM
INPUT
CHANNELS
TO FARM
(OUTPUT SIDE)
S/PDIF Tx
S/PDIF Rx
SPDIFI
SPDIFO
ASRC I/O
(16 CH)
SERIAL I/O
(24 CH)
S/PDIF I/O
(2 CH)
DSP CORE
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
IN
F
R
O
M
AS
RCs
O
UT
T
O
AS
RCs
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
16, 17
18, 19
20, 21
22, 23
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
16, 17
18, 19
20, 21
22, 23
07
69
6-
0
46
Figure 45. DSP Core Input and Output Signals
Some algorithms running inside the SigmaStudio signal flow
may mix or split channels within the DSP. Therefore, the
number of output pairs does not necessarily have to equal the
number of input pairs.
Note that, while the S/PDIF Rx pair can be routed either to the
FARM input side or directly to the DSP, the S/PDIF Tx pair
must be routed directly to the S/PDIF output pin (SPDIFO),
bypassing the FARM output side.
The ASRC I/O block in Figure 45 represents the interaction
between the DSP and the ASRCs. Inputs to the DSP from the
ASRCs (ASRC-to-DSP pairs) are represented in SigmaStudio as
ASRC input cells, whereas outputs to the ASRCs from the DSP
(DSP-to-ASRC pairs) are represented in SigmaStudio as ASRC
output cells. The cells are shown in their respective locations in
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
ASRC I/O
(16 CH)
IN
F
RO
M
AS
RC
s
OU
T
TO
A
S
R
C
s
07
69
6-
0
47
Figure 46. ASRC Input and Output Cells
相關(guān)PDF資料
PDF描述
VI-B6Z-MW CONVERTER MOD DC/DC 2V 40W
VI-233-CU-F1 CONVERTER MOD DC/DC 24V 200W
ADAU1445YSVZ-3A IC SIGMADSP 175MHZ 100TQFP
VI-232-IW-S CONVERTER MOD DC/DC 15V 100W
AD1941YSTZ IC DSP AUDIO 16CHAN 28BIT 48LQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADAU1442YSVZ-3A-RL 功能描述:IC SIGMADSP 28B 175MHZ 100TQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
ADAU1445YSVZ-3A 功能描述:IC SIGMADSP 175MHZ 100TQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
ADAU1445YSVZ-3A-RL 功能描述:IC SIGMADSP 175MHZ 100TQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
ADAU1446EBZ 制造商:Analog Devices 功能描述:SIGMADSP? DIGITAL AUDIO PROCESSOR WITH FLEXIBLE AUDIO - Bulk
ADAU1446YSTZ-3A 功能描述:IC SIGMADSP 175MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*