參數(shù)資料
型號: AD9991KCPRL
廠商: ANALOG DEVICES INC
元件分類: 消費家電
英文描述: 10-Bit CCD Signal Processor with Precision Timing Generator
中文描述: SPECIALTY CONSUMER CIRCUIT, QCC56
封裝: 8 X 8 MM, MO-220-VLLD-2, LFCSP-56
文件頁數(shù): 51/60頁
文件大?。?/td> 826K
代理商: AD9991KCPRL
AD9991
–51–
Table XL. V-Sequence 3 (VSEQ3) Register Map
Data Bit Default
Address Content Value Register Name Description
98 [1:0] 0 HBLKMASK_3 Masking Polarity during HBLK. H1 [0]. H3 [1].
[2] 0 CLPOBPOL_3 CLPOB Start Polarity
[3] 0 PBLKPOL_3 PBLK Start Polarity
[7:4] 0 VPATSEL_3 Selected V-Pattern Group for V-Sequence 3
[9:8] 0 VMASK_3 Enable Masking of V-Outputs (Specified by Freeze/Resume Registers)
[11:10] 0 HBLKALT_3 Enable HBLK Alternation
[23:12] 0 UNUSED Unused
99 [11:0] 0 VPATREPO_3 Number of Selected V-Pattern Group Repetitions for Odd Lines
[23:12] 0 VPATREPE_3 Number of Selected V-Pattern Group Repetitions for Even Lines
9A [11:0] 0 VPATSTART_3 Start Position in the Line for the Selected V-Pattern Group
[23:12] 0 HDLEN_3 HD Line Length (Number of Pixels) for V-Sequence 3
9B [11:0] 0 PBLKTOG1_3 PBLK Toggle Position 1 for V-Sequence 3
[23:12] 0 PBLKTOG2_3 PBLK Toggle Position 2 for V-Sequence 3
9C [11:0] 0 HBLKTOG1_3 HBLK Toggle Position 1 for V-Sequence 3
[23:12] 0 HBLKTOG2_3 HBLK Toggle Position 2 for V-Sequence 3
9D [11:0] 0 HBLKTOG3_3 HBLK Toggle Position 3 for V-Sequence 3
[23:12] 0 HBLKTOG4_3 HBLK Toggle Position 4 for V-Sequence 3
9E [11:0] 0 HBLKTOG5_3 HBLK Toggle Position 5 for V-Sequence 3
[23:12] 0 HBLKTOG6_3 HBLK Toggle Position 6 for V-Sequence 3
9F [11:0] 0 CLPOBTOG1_3 CLPOB Toggle Position 1 for V-Sequence 3
[23:12] 0 CLPOBTOG2_3 CLPOB Toggle Position 2 for V-Sequence 3
Table XLI. V-Sequence 4 (VSEQ4) Register Map
Data Bit Default
Address Content Value Register Name Description
A0 [1:0] 0 HBLKMASK_4 Masking Polarity during HBLK. H1 [0]. H3 [1].
[2] 0 CLPOBPOL_4 CLPOB Start Polarity
[3] 0 PBLKPOL_4 PBLK Start Polarity
[7:4] 0 VPATSEL_4 Selected V-Pattern Group for V-Sequence 4
[9:8] 0 VMASK_4 Enable Masking of V-Outputs (Specified by Freeze/Resume Registers)
[11:10] 0 HBLKALT_4 Enable HBLK Alternation
[23:12] 0 UNUSED Unused
A1 [11:0] 0 VPATREPO_4 Number of Selected V-Pattern Group Repetitions for Odd Lines
[23:12] 0 VPATREPE_4 Number of Selected V-Pattern Group Repetitions for Even Lines
A2 [11:0] 0 VPATSTART_4 Start Position in the Line for the Selected V-Pattern Group
[23:12] 0 HDLEN_4 HD Line Length (Number of Pixels) for V-Sequence 4
A3 [11:0] 0 PBLKTOG1_4 PBLK Toggle Position 1 for V-Sequence 4
[23:12] 0 PBLKTOG2_4 PBLK Toggle Position 2 for V-Sequence 4
A4 [11:0] 0 HBLKTOG1_4 HBLK Toggle Position 1 for V-Sequence 4
[23:12] 0 HBLKTOG2_4 HBLK Toggle Position 2 for V-Sequence 4
A5 [11:0] 0 HBLKTOG3_4 HBLK Toggle Position 3 for V-Sequence 4
[23:12] 0 HBLKTOG4_4 HBLK Toggle Position 4 for V-Sequence 4
A6 [11:0] 0 HBLKTOG5_4 HBLK Toggle Position 5 for V-Sequence 4
[23:12] 0 HBLKTOG6_4 HBLK Toggle Position 6 for V-Sequence 4
A7 [11:0] 0 CLPOBTOG1_4 CLPOB Toggle Position 1 for V-Sequence 4
[23:12] 0 CLPOBTOG2_4 CLPOB Toggle Position 2 for V-Sequence 4
REV. 0
相關(guān)PDF資料
PDF描述
AD9991KCP 10-Bit CCD Signal Processor with Precision Timing Generator
AD9991 10-Bit CCD Signal Processor with Precision Timing Generator
AD9992 12-Bit CCD Signal Processor with Precision Timing Generator
AD9992BBCZ 12-Bit CCD Signal Processor with Precision Timing Generator
AD9992BBCZRL 12-Bit CCD Signal Processor with Precision Timing Generator
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