參數(shù)資料
型號(hào)： AD9991KCPRL
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： 10-Bit CCD Signal Processor with Precision Timing Generator
中文描述： SPECIALTY CONSUMER CIRCUIT, QCC56
封裝： 8 X 8 MM, MO-220-VLLD-2, LFCSP-56
文件頁(yè)數(shù)： 13/60頁(yè)
文件大小： 826K
代理商： AD9991KCPRL
AD9991
–13–
HORIZONTAL CLAMPING AND BLANKING
The AD9991’s horizontal clamping and blanking pulses are fully
programmable to suit a variety of applications. Individual control
is provided for CLPOB, PBLK, and HBLK during the different
regions of each field. This allows the dark pixel clamping and
blanking patterns to be changed at each stage of the readout in
order to accommodate different image transfer timing and high
speed line shifts.
Individual CLPOB and PBLK Patterns
The AFE horizontal timing consists of CLPOB and PBLK, as
shown in Figure 9. These two signals are independently pro-
grammed using the registers in Table III. SPOL is the start
polarity for the signal, and TOG1 and TOG2 are the first and
second toggle positions of the pulse. Both signals are active low
and should be programmed accordingly.
A separate pattern for CLPOB and PBLK may be programmed
for each 10 V-sequence. As described in the Vertical Timing Gen-
eration section, up to 10 separate V-sequences can be created,
each containing a unique pulse pattern for CLPOB and PBLK.
Figure 9 shows how the sequence change positions divide the
readout field into different regions. A different V-Sequence can be
assigned to each region, allowing the CLPOB and PBLK signals
to be changed accordingly with each change in the vertical timing.
Individual HBLK Patterns
The HBLK programmable timing shown in Figure 10 is simi-
lar to CLPOB and PBLK. However, there is no start polarity
control. Only the toggle positions are used to designate the start
and stop positions of the blanking period. Additionally, there is a
polarity control HBLKMASK that designates the polarity of the
horizontal clock signals H1–H4 during the blanking period. Set-
ting HBLKMASK high will set H1 = H3 = Low and H2 = H4 =
High during the blanking, as shown in Figure 11. As with the
CLPOB and PBLK signals, HBLK registers are available in each
V-sequence, allowing different blanking signals to be used with
different vertical timing sequences.
(3)
(2)
(1)
HD
CLPOB
PBLK
. . .
NOTES
PROGRAMMABLE SETTINGS:
(1) START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW)
(2) FIRST TOGGLE POSITION
(3) SECOND TOGGLE POSITION
. . .
ACTIVE
ACTIVE
Figure 9. Clamp and Pre-Blank Pulse Placement
Table III. CLPOB and PBLK Pattern Registers
Range
High/Low
0–4095 Pixel Location
0–4095 Pixel Location
Register
SPOL
TOG1
TOG2
Length
1b
12b
12b
Description
Starting Polarity of CLPOB/PBLK for V-Sequence 0–9
First Toggle Position within Line for V-Sequence 0–9
Second Toggle Position within Line for V-Sequence 0–9
Table IV. HBLK Pattern Registers
Register
HBLKMASK
HBLKALT
HBLKTOG1
HBLKTOG2
HBLKTOG3
HBLKTOG4
HBLKTOG5
HBLKTOG6
Length
1b
2b
12b
12b
12b
12b
12b
12b
Range
High/Low
0–3 Alternation Mode
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
Description
Masking Polarity for H1/H3 (0 = H1/H3 Low, 1 = H1/H3 High)
Enables Odd/Even Alternation of HBLK Toggle Positions 0 =
Disable Alternation. 1 = TOG1–TOG2 Odd, TOG3–TOG6 Even.
2 = 3 = TOG1–TOG2 Even, TOG3–TOG6 Odd
First Toggle Position within Line for Each V-Sequence 0–9
Second Toggle Position within Line for Each V-Sequence 0–9
Third Toggle Position within Line for Each V-Sequence 0–9
Fourth Toggle Position within Line for Each V-Sequence 0–9
Fifth Toggle Position within Line for Each V-Sequence 0–9
Sixth Toggle Position within Line for Each V-Sequence 0–9
REV. 0
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