參數(shù)資料
型號(hào)： AD9985KSTZ-140
廠商： ANALOG DEVICES INC
元件分類： 其它接口
英文描述： 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays
中文描述： SPECIALTY INTERFACE CIRCUIT, PQFP80
封裝： LEAD FREE, MS-026BEC, LQFP-80
文件頁(yè)數(shù)： 19/32頁(yè)
文件大?。?/td> 349K
代理商： AD9985KSTZ-140
AD9985
Rev. 0 | Page 19 of 32
2-WIRE SERIAL CONTROL REGISTER DETAIL CHIP
IDENTIFICATION
00
7–0
Chip Revision
An 8-bit register that represents the silicon revision.
PLL DIVIDER CONTROL
01
7–0
The 8 most significant bits of the 12-bit PLL divide
ratio PLLDIV. The operational divide ratio is
PLLDIV + 1.
PLL Divide Ratio MSBs
The PLL derives a master clock from an incoming
Hsync signal. The master clock frequency is then
divided by an integer value, such that the output is
phase-locked to Hsync. This PLLDIV value
determines the number of pixel times (pixels plus
horizontal blanking overhead) per line. This is
typically 20% to 30% more than the number of active
pixels in the display.
The 12-bit value of the PLL divider supports divide
ratios from 2 to 4095. The higher the value loaded in
this register, the higher the resulting clock frequency
with respect to a fixed Hsync frequency.
VESA has established some standard timing
specifications that assist in determining the value for
PLLDIV as a function of horizontal and vertical
display resolution and frame rate (Table 9).
However, many computer systems do not conform
precisely to the recommendations, and these numbers
should be used only as a guide. The display system
manufacturer should provide automatic or manual
means for optimizing PLLDIV. An incorrectly set
PLLDIV will usually produce one or more vertical
noise bars on the display. The greater the error, the
greater the number of bars produced.
The power-up default value of PLLDIV is 1693
(PLLDIVM = 69H, PLLDIVL = DxH).
The AD9985 updates the full divide ratio only when
the LSBs are changed. Writing to the MSB by itself will
not trigger an update.
02
7–4 PLL Divide Ratio LSBs
The 4 least significant bits of the 12-bit PLL divide
ratio PLLDIV. The operational divide ratio is
PLLDIV + 1.
The power-up default value of PLLDIV is 1693
(PLLDIVM = 69H, PLLDIVL = DxH). The AD9985
updates the full divide ratio only when this register is
written to.
CLOCK GENERATOR CONTROL
03
7–6
VCO Range Select
Two bits that establish the operating range of the clock
generator.
VCORNGE must be set to correspond with the
desired operating frequency (incoming pixel rate).
The PLL gives the best jitter performance at high
frequencies. For this reason, to output low pixel rates
and still get good jitter performance, the PLL actually
operates at a higher frequency but then divides down
the clock rate afterwards.
Table 11 shows the pixel rates for each VCO range setting. The
PLL output divisor is automatically selected with the
VCO range setting.
Table 11. VCO Ranges
PV1
PV0
0
0
0
1
1
0
1
1
Pixel Clock Range (MHz)
AD9985KSTZ
12–32
32–64
64–110
110–140
AD9985BSTZ
12–30
30–60
60–110
The power-up default value is 01.
03
5–3
Three bits that establish the current driving the loop
filter in the clock generator.
Table 12. Charge Pump Currents
CURRENT
Current (μA)
CURRENT Charge Pump Current
000
001
010
011
100
101
110
111
50
100
150
250
350
500
750
1500
CURRENT must be set to correspond with the desired
operating frequency (incoming pixel rate).
The power-up default value is current = 001.
04
7–3
A 5-bit value that adjusts the sampling phase in 32
steps across one pixel time. Each step represents an
11.25° shift in sampling phase.
Clock Phase Adjust
The power-up default value is 16.
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