參數(shù)資料
型號(hào)： AD9984AKSTZ-170
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 31/44頁(yè)
文件大?。?/td> 0K
描述： IC DISPLAY 10BIT 170MSPS 80LQFP
標(biāo)準(zhǔn)包裝： 1
類型： 接口
應(yīng)用： 顯示器，處理，電視
安裝類型： 表面貼裝
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-LQFP（14x14）
包裝： 托盤
AD9984A
Rev. 0 | Page 37 of 44
0x20—Bit[0]
Must be set to 1 for proper operation.
0x21—Bits[7:0]
Must be set to default.
0x22—Bits[7:0]
Must be set to default.
0x23—Bits[7:0] Sync Filter Window Width
This 8-bit register sets the window of time for the regenerated
Hsync leading edge (in 25 ns steps) and the time that sync
pulses are allowed to pass through. Therefore, with the
default value of 10, the window width is ±250 ns. The goal is
to set the window width to reject extraneous pulses (see the
Sync Processing section). As with the sync separator threshold,
the 25 ns multiplier value is somewhat variable. The maximum
variability over all operating conditions is ±20% (20 ns to 30 ns).
DETECTION STATUS
0x24—Bit[7] HSYNC0 Detection
This bit is used to indicate when activity is detected on the
HSYNC0 input pin. If HSYNC0 is held high or low, activity is
not detected. The sync processing block diagram (Figure 9)
shows where this function is implemented.
Table 62. HSYNC0 Detection Bit
Value
Result
0
No activity detected.
1
Activity detected.
0x24—Bit[6] HSYNC1 Detection
This bit is used to indicate when activity is detected on the
HSYNC1 input pin. If HSYNC1 is held high or low, activity is
not detected. Figure 9 shows where this function is implemented.
Table 63. HSYNC1 Detection Results
Value
Result
0
No activity detected.
1
Activity detected.
0x24—Bit[5] VSYNC0 Detection
This bit is used to indicate when activity is detected on the
VSYNC0 input pin. If VSYNC0 is held high or low, activity is
not detected. Figure 9 shows where this function is implemented.
Table 64. VSYNC0 Detection Results
Value
Result
0
No activity detected.
1
Activity detected.
0x24—Bit[4] VSYNC1 Detection
This bit is used to indicate when activity is detected on the
VSYNC1 input pin. If VSYNC1 is held high or low, activity is
not detected. Figure 9 shows where this function is implemented.
Table 65. VSYNC1 Detection Bit
Value
Result
0
No activity detected.
1
Activity detected.
0x24—Bit[3] SOGIN0 Detection
This bit is used to indicate when activity is detected on the
SOGIN0 pin. If SOGIN0 is held high or low, activity is not
detected. Figure 9 shows where this function is implemented.
Table 66. SOGIN0 Detection Bit
Value
Result
0
No activity detected.
1
Activity detected.
0x24—Bit[2] SOGIN1 Detection
This bit is used to indicate when activity is detected on the
SOGIN1 input pin. If SOGIN1 is held high or low, activity is not
detected. Figure 9 shows where this function is implemented.
Table 67. SOGIN1 Detection Bit
Value
Result
0
No activity detected.
1
Activity detected.
0x24—Bit[1] COAST Detection
This bit detects activity on the EXTCK/COAST pin. It indicates
that one of the two signals is active, but it does not indicate
which one. A dc signal is not detected.
Table 68. COAST Detection Bit
Value
Result
0
No activity detected.
1
Activity detected.
0x24—Bit[0] CLAMP Detection
This bit is used to indicate when activity is detected on the
external CLAMP pin. If external CLAMP is held high or low,
activity is not detected.
Table 69. CLAMP Detection Bit
Value
Result
0
No activity detected.
1
Activity detected.
POLARITY STATUS
0x25—Bit[7] HSYNC0 Polarity
This bit indicates the polarity of HSYNC0 input.
Table 70. HSYNC0 Polarity Bit
Value
Result
0
HSYNC0 polarity is negative.
1
HSYNC0 polarity is positive.
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