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參數(shù)資料
| 型號(hào)： | AD9984AKSTZ-170 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 21/44頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DISPLAY 10BIT 170MSPS 80LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 接口 |
| 應(yīng)用： | 顯示器，處理，電視 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-LQFP（14x14） |
| 包裝： | 托盤 |
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AD9984A
Rev. 0 | Page 28 of 44
Hex
Address
Read/Write,
Read Only
Bits
Default
Value
Register Name
Description
6
*_** ****
HSYNC1 Detection.
0 = HSYNC1 is not active.
1 = HSYNC1 is active.
5
**_* ****
VSYNC0 Detection.
0 = VSYNC0 is not active.
1 = VSYNC0 is active.
4
***_ ****
VSYNC1 Detection.
0 = VSYNC1 is not active.
1 = VSYNC1 is active.
3
**** _***
SOGIN0 Detection.
0 = SOGIN0 is not active.
1 = SOGIN0 is active.
2
**** *_**
SOGIN1 Detection.
0 = SOGIN1 is not active.
1 = SOGIN1 is active.
1
**** **_*
COAST Detection.
0 = External COAST is not active.
1 = External COAST is active.
0
**** ***_
CLAMP Detection.
0 = External CLAMP is not active.
1 = External CLAMP is active.
0x25
RO
7
_*** ****
Sync Polarity Detect
HSYNC0 Polarity.
0 = HSYNC0 polarity is negative.
1 = HSYNC0 polarity is positive.
6
*_** ****
HSYNC1 Polarity.
0 = HSYNC1 polarity is negative.
1 = HSYNC1 polarity is active high.
5
**_* ****
VSYNC0 Polarity.
0 = VSYNC0 polarity is negative.
1 = VSYNC0 polarity is positive.
4
***_ ****
VSYNC1 Polarity.
0 = VSYNC1 polarity is negative.
1 = VSYNC1 polarity is positive.
3
**** _***
COAST Polarity.
0 = External COAST is negative.
1 = External COAST is positive.
2
**** *_**
CLAMP Polarity.
0 = External CLAMP is negative.
1 = External CLAMP polarity is positive.
1
**** **_*
Extraneous Pulse Detection.
0 = No extraneous pulses detected on Hsync.
1 = Extraneous pulses detected on Hsync.
0
**** ***_
Sync Filter Lock.
0 = Sync filter unlocked
1 = Sync filter locked.
0x26
RO
7:0
Hsyncs per
Vsync MSBs
MSBs of Hsyncs per Vsync count.
0x27
RO
7:4
Hsyncs per
Vsync LSBs
LSBs of Hsyncs per Vsync count.
0x28
R/W
7:0
1011 1111
Test Register 1
Must be written to 0xBF for proper operation.
0x29
R/W
7:0
0000 0010
Test Register 2
Must be written to 0x02 for proper operation.
0x2A
RO
7:0
Test Register 3
Read only bits for future use.
0x2B
RO
7:0
Test Register 4
Read only bits for future use.
0x2C
R/W
7:5
000* ****
Offset Hold
Must be written to default for proper operation.
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