參數(shù)資料
型號(hào)： AD9983AKSTZ-1701
廠商： Analog Devices, Inc.
英文描述： High Performance 8-Bit Display Interface
中文描述： 高性能8位顯示接口
文件頁(yè)數(shù)： 27/44頁(yè)
文件大?。?/td> 470K
代理商： AD9983AKSTZ-1701
Preliminary Technical Data
AD9983A
Hex
Address
Rev. PrA | Page 27 of 44
Read/Write,
Read Only
Bits
3
Default
Value
**** 0***
Register Name
Description
Power-Down.
0 = Normal operation
1 = Power-down
Power-Down Pin Polarity.
0 = Active low
1 = Active high
Power-Down Fast Switching Control.
0 = Normal power-down operation
1 = The chip stays powered up and the outputs are put in high
impedance mode
SOGOUT High Impedance Control.
0 = SOGOUT operates as normal during power-down
1 = SOGOUT is in high impedance during power-down
Output Mode.
100 = 4:4:4 output mode
101 = 4:2:2 output mode
110 = 4:4:4—DDR output mode
Primary Output Enable.
0 = Primary output is in high impedance state
1 = Primary output is enabled
Secondary Output Enable.
0 = Secondary output is in high impedance state
1 = Secondary output is enabled
Output Drive Strength.
00 = Low output drive strength
01 = Medium output drive strength
10 = High output drive strength
11 = High output drive strength
Applies to all outputs except VSOUT.
Output Clock Invert.
0 = Noninverted pixel clock
1 = Inverted pixel clock
Applies to all clocks output on DATACK.
Output Clock Select.
00 = Pixel clock
01 = 90° phase shifted pixel clock
10 = 2× pixel clock
11 = 0.5× pixel clock
Output High Impedance.
0 = Normal outputs
1 = All outputs except SOGOUT in high impedance mode
SOG High Impedance.
0 = Normal SOG output
1 = SOGOUT pin is in high impedance mode
Field Output Polarity. Sets the polarity of the field output signal.
0 = Active low => even field, active high => odd field
1 = Active low => odd field, active high => even field
PLL Sync Filter Enable.
0 = PLL uses raw Hsync/SOG
1 = PLL uses filtered Hsync/SOG
Sync Processing Input Select. Selects the sync source for the sync
processor.
0 = Sync processing uses raw Hsync/SOGIN
1 = Sync processing uses regenerated Hsync from sync filter
Must be set to 1 for proper operation.
Must be set to default for proper operation.
Must be set to default for proper operation.
2
**** *0**
1
**** **0*
0
**** ***0
0x1F
R/W
7:5
100* ****
Output Select 1
4
***1 ****
3
**** 0***
2:1
**** *10*
0
**** ***0
0x20
R/W
7:6
0*** ****
Output Select 2
5
*0** ****
4
**0* ****
3
***0 ****
2
**** 1***
1
**** *0**
0x21
0x22
R/W
R/W
0
7:0
7:0
0010 0000
0011 0010
相關(guān)PDF資料
PDF描述
AD9983A High Performance 8-Bit Display Interface
AD9983AKCPZ-140 High Performance 8-Bit Display Interface
AD9983AKCPZ-1401 High Performance 8-Bit Display Interface
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AD9983AKCPZ-1701 High Performance 8-Bit Display Interface
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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