參數(shù)資料
型號(hào): AD9983AKSTZ-1701
廠商: Analog Devices, Inc.
英文描述: High Performance 8-Bit Display Interface
中文描述: 高性能8位顯示接口
文件頁(yè)數(shù): 26/44頁(yè)
文件大?。?/td> 470K
代理商: AD9983AKSTZ-1701
AD9983A
Preliminary Technical Data
Hex
Address
Rev. PrA | Page 26 of 44
Read/Write,
Read Only
Bits
4
Default
Value
***0 ****
Register Name
Description
Clamp Source Select.
0 = Use the internal clamp generated from Hsync
1 = Use the external clamp signal
Red Clamp Select.
0 = Clamp the red channel to ground
1 = Clamp the red channel to midscale
Green Clamp Select.
0 = Clamp the green channel to ground
1 = Clamp the green channel to midscale
Blue Clamp Select.
0 = Clamp the blue channel to ground
1 = Clamp the blue channel to midscale
Must be set to 0 for proper operation.
Places the clamp signal an integer number of clock periods after
the trailing edge of the Hsync signal.
Number of clock periods that the clamp signal is actively clamping.
External Clamp Polarity Override.
0 = The chip selects the clamp polarity
1 = The polarity of the clamp signal is set by Reg. 0x1B, Bit 6
External Clamp Input Polarity. This bit is used only if Reg. 0x1B, Bit 7
is set to 1.
0 = Active low external clamp
1 = Active high external clamp
Auto-Offset Enable.
0 = Auto-offset is disabled
1 = Auto-offset is enabled (offsets become the desired clamp code)
Auto-Offset Update Frequency. This selects how often the auto-
offset circuit operates.
00 = every 3 clamps
01 = 48 clamps
10 = every 192 clamps
11 = every 3 Vsyncs
Must be written to default (011) for proper operation.
Must be set to 0xFF for proper operation.
SOG Slicer Threshold. Sets the voltage level of the SOG slicer’s
comparator.
SOGOUT Polarity. Sets the polarity of the signal on the SOGOUT pin.
0 = Active low SOGOUT
1 = Active high SOGOUT
SOGOUT Select.
00 = Raw SOG from sync slicer (SOGIN0 or SOGIN1)
01 = Raw Hsync (HSYNC0 or HSYNC1)
10 = Regenerated sync from sync filter
11 = Filtered sync from sync filter
Channel Select Override.
0 = The chip determines which input channels to use
1 = The input channel selection is determined by Reg. 0x1E, Bit 6
Channel Select. Input channel select: this is used only if Reg. 0x1E,
Bit 7 is set to 1, or if syncs are present on both channels.
0 = Channel 0 syncs and data are selected
1 = Channel 1 syncs and data are selected
Programmable Bandwidth.
0 = Low analog input bandwidth (7 MHz)
1 = High analog input bandwidth
Power-Down Control Select.
0 = Manual power-down control
1 = Auto power-down control
3
**** 0***
2
**** *0**
1
**** **0*
0x19
R/W
0
7:0
**** ***0
0000 1000
Clamp Placement
0x1A
0x1B
R/W
R/W
7:0
7
0010 0000
0*** ****
Clamp Duration
Clamp and Offset
6
*1** ****
5
**0* ****
4:3
***1 1***
0x1C
0x1D
R/W
R/W
2:0
7:0
7:3
**** *011
1111 1111
0111 1***
TestReg0
SOG Control
2
**** *0**
1:0
**** **00
0x1E
R/W
7
*** ****
Power
6
*0** ****
5
**1* ****
4
***1 ****
相關(guān)PDF資料
PDF描述
AD9983A High Performance 8-Bit Display Interface
AD9983AKCPZ-140 High Performance 8-Bit Display Interface
AD9983AKCPZ-1401 High Performance 8-Bit Display Interface
AD9983AKCPZ-170 High Performance 8-Bit Display Interface
AD9983AKCPZ-1701 High Performance 8-Bit Display Interface
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9983KSTZ-110 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:
AD9983KSTZ-140 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:
AD9983KSTZ-170 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:
AD9984A 制造商:AD 制造商全稱:Analog Devices 功能描述:High Performance 10-Bit Display Interface
AD9984A/PCB 制造商:Analog Devices 功能描述:DISPLAY INTRFC - Bulk