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AD9981
0x21
Rev. 0 | Page 37 of 44
7:0
Must be set to default
0x22
7:0
Must be set to default
0x23
7:0
Sync Filter Window Width
This 8-bit register sets the window of time for the regenerated
Hsync leading edge (in 25 ns steps) and that sync pulses are
allowed to pass through. Therefore with the default value of 10,
the window width is ±250 ns. The goal is to set the window
width so that extraneous pulses are rejected. (see the Sync
Processing section). As in the sync separator threshold, the
25 ns multiplier value is somewhat variable. The maximum
variability over all operating conditions is ±20% (20 ns
to 30 ns).
DETECTION STATUS
0x24
7
Hsync0 Detection Bit
This bit is used to indicate when activity is detected on
the HSYNC0 input pin. If Hsync is held high or low,
activity is not detected. The sync processing block
diagram shows where this function is implemented.
0 = Hsync0 not active. 1 = Hsync0 is active.
Table 54. Hsync0 Detection Results
Detect
Result
0
No activity detected
1
Activity detected
0x24
6
Hsync1 Detection Bit
This bit is used to indicate when activity is detected on
the HSYNC1 input pin. If HSYNC is held high or low,
activity is not detected. The sync processing block
diagram shows where this function is implemented.
0 = HSYNC1 not active. 1 = HSYNC1 is active.
Table 55. Hsync1 Detection Results
Detect
Result
0
No activity detected
1
Activity detected
0x24
5
Vsync0 Detection Bit
This bit is used to indicate when activity is detected on
the VSYNC0 input pin. If Vsync is held high or low,
activity is not detected. The sync processing block
diagram shows where this function is implemented.
0 = Vsync0 not active. 1 = Vsync0 is active.
Table 56. Vsync0 Detection Results
Detect
Result
0
No activity detected
1
Activity detected
0x24
4
VSYNC1 Detection Bit
This bit is used to indicate when activity is detected on
the VSYNC1 input pin. If Vsync is held high or low,
activity is not detected. The sync processing block
diagram shows where this function is implemented.
0 = Vsync1 not active. 1 = Vsync1 is active.
Table 57. Vsync1 Detection Results
Detect
Result
0
No activity detected
1
Activity detected
0x24
3
SOG0 Detection Bit
This bit is used to indicate when activity is detected on
the SOG0 input pin. If SOG is held high or low,
activity is not detected. The sync processing block
diagram shows where this function is implemented.
0 = SOG0 not active. 1 = SOG0 is active.
Table 58. SOG0 Detection Results
Detect
Result
0
No activity detected
1
Activity detected
0x24
2
SOG1 Detection Bit
This bit is used to indicate when activity is detected on
the SOG1 input pin. If SOG is held high or low,
activity is not detected. The sync processing block
diagram shows where this function is implemented.
0 = SOG1 not active. 1 = SOG1 is active.
Table 59. SOG1 Detection Results
Detect
Result
0
No activity detected
1
Activity detected
0x24
1
COAST Detection Bit
This bit detects activity on the EXTCLK/EXTCOAST
pin. It indicates that one of the two signals is active,
but it doesn’t indicate which one. A dc signal is
not detected.
Table 60. Coast Detection Result
Detect
Result
0
No activity detected
1
Activity detected
0x24
0
Clamp Detection Bit
This bit is used to indicate when activity is detected on
the external CLAMP pin. If external clamp is held
high or low, activity is not detected.
Table 61. Clamp Detection Results
Detect
Result
0
No activity detected
1
Activity detected