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參數(shù)資料
| 型號： | AD9981 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | High Performance 10-Bit Display Interface |
| 中文描述： | 高性能10位顯示接口 |
| 文件頁數(shù)： | 33/44頁 |
| 文件大?。?/td> | 506K |
| 代理商： | AD9981 |
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AD9981
Table 28. Coast Source Selection Settings
Select
0
1
Rev. 0 | Page 33 of 44
Result
Vsync (internal Coast)
COAST input pin
0x18
6
Coast Polarity Override
This register is used to override the internal circuitry
that determines the polarity of the Coast signal going
into the PLL. The power-up default setting is 0.
Table 29. Coast Polarity Override Settings
Override Bit
Result
0
Coast polarity determined by chip
1
Coast polarity determined by user
0x18
5
Input Coast Polarity
This register sets the input Coast polarity when Bit 6
of Register 0x18 = 1. The power-up default setting is 1.
Table 30. Coast Polarity Settings
Coast Polarity Bit
Result
0
Coast polarity is negative
1
Coast polarity is positive
0x18
4
Clamp Source
This bit determines the source of clamp timing. A 0
enables the clamp timing circuitry controlled by
clamp placement and clamp duration. The clamp posi-
tion and duration is counted from the leading edge of
Hsync. A 1 enables the external clamp input pin. The
three channels are clamped when the clamp signal is
active. The polarity of clamp is determined by the
clamp polarity bit. The power-up default setting
is 0.
Table 31. Clamp Source Selection Settings
Clamp Source
Result
0
Internally generated clamp
1
Externally provided clamp signal
0x18
3
Red Clamp Select
This bit determines whether the red channel is
clamped to ground or to midscale. The power-up
default setting is 0.
Table 32. Red Clamp Select Settings
Clamp
Result
0
Clamp to ground
1
Clamp to midscale
0x18
2
Green Clamp Select
This bit determines whether the green channel is
clamped to ground or to midscale. The power-up
default setting is 0.
Table 33. Green Clamp Select Settings
Clamp
0
1
Result
Clamp to ground
Clamp to midscale
0x18
1
Blue Clamp Select
This bit determines whether the blue channel is
clamped to ground or to midscale. The power-up
default setting is 0.
Table 34. Blue Clamp Select Settings
Clamp
Result
0
Clamp to ground
1
Clamp to midscale
0x19
7:0
Clamp Placement
An 8-bit register that sets the position of the internally
generated clamp. When EXTCLMP = 0 (Register 0x18,
Bit 4), a clamp signal is generated internally, at a
position established by the clamp placement register
(Register 0x19) and for a duration set by the clamp
duration register (Register 0x1A). Clamping is started
a clamp placement count(Register 0x19) of pixel
periods after the trailing edge of Hsync. The clamp
placement may be programmed to any value between
1 and 255. A value of 0 is not supported.
The clamp should be placed during a time that the
input signal presents a stable black-level reference,
usually the back porch period between Hsync and the
image. When EXTCLMP = 1, this register is ignored.
Power-up default setting is 8.
0x1A
7:0
Clamp Duration
An 8-bit register that sets the duration of the
internally generated clamp. When EXTCLMP = 0
(Register 0x18, Bit 4), a clamp signal is generated
internally at a position established by the clamp
placement register (and for a duration set by the
clamp duration register). Clamping begins a clamp
placement count (Register 0x19) of pixel periods after
the trailing edge of Hsync. The clamp duration may be
programmed to any value between 1 and 255. A value
of 0 is not supported.
For the best results, the clamp duration should be set
to include the majority of the black reference signal
time that follows the Hsync signal trailing edge. Insuf-
ficient clamping time can produce brightness changes
at the top of the screen, and a slow recovery from large
changes in the average picture level (APL), or bright-
ness. When EXTCLMP = 1, this register is ignored.
Power-up default setting is 20 DDR.
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| AD9981KSTZ-80 | High Performance 10-Bit Display Interface |
| AD9981KSTZ-95 | High Performance 10-Bit Display Interface |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9981/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Performance 10-Bit Display Interface |
| AD9981/PCBZ | 制造商:Analog Devices 功能描述:Evaluation Board For The High Performance 10-Bit Display Interface 制造商:Analog Devices 功能描述:EVAL BD FOR THE HI-PERF 10-BIT DISPLAY INTRFC - Bulk |
| AD9981KST-80 | 制造商:Analog Devices 功能描述:HIGH PERFORMANCE 10-BIT DISPLAY INTERFACE - Bulk |
| AD9981KSTZ-80 | 功能描述:IC INTERFACE 10BIT ANALOG 80LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9981KSTZ-95 | 功能描述:IC INTERFACE 10BIT ANALOG 80LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
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