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參數(shù)資料
| 型號： | AD9975ABSTEB |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | DC/DC變換器 |
| 英文描述： | RP10 (E) Series - Powerline Regulated DC-DC Converters; Input Voltage (Vdc): 48V; Output Voltage (Vdc): 5V; 2:1 Wide Input Voltage Range; 10 Watts Output Power; 1.6kVDC Isolation; UL Certified; Fixed Operating Frequency; Six-Sided Continuous Shield; Standard 50.8 x25.4x10.2mm Package; Efficiency to 86% |
| 中文描述： | 寬帶調(diào)制解調(diào)器混合信號前端 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 1392K |
| 代理商： | AD9975ABSTEB |
REV. 0
–2–
AD9975–SPECIFICATIONS
Test
Level
Parameter
Temp
Min
Typ
Max
Unit
OSC IN CHARACTERISTICS
Frequency Range
Duty Cycle
Input Capacitance
Input Impedance
Full
25
°
C
25
°
C
25
°
C
I
II
III
III
10
40
50
60
MHz
%
pF
M
50
3
100
CLOCK OUTPUT CHARACTERISTICS
CLKA Jitter (F
CLKA
Derived from PLL)
CLKA Duty Cycle
25
°
C
25
°
C
II
III
14
50
±
5
ps rms
%
TX CHARACTERISTICS
2
×
Interpolation Filter Characteristics
TX Path Latency, 2
×
Interpolation
Pass-Band Flatness 0 MHz to 20.7 MHz
Stop-Band Rejection @ 29.3 MHz
TxDAC
Resolution
Conversion Rate
Full-Scale Output Current
Voltage Compliance Range (TX+ or TX– AVSS) Full
Gain Error
Output Offset
Differential Nonlinearity
Integral Nonlinearity
Output Capacitance
Phase Noise @ 1 kHz Offset, 10 MHz Signal
Signal-to-Noise and Distortion (SINAD)
5 MHz Analog Out (20 MHz BW)
Wideband SFDR (to Nyquist, 50 MHz max)
5 MHz Analog Out
Narrowband SFDR (3 MHz Window)
5 MHz Analog Out
IMD (f1 = 6.25 MHz, f2 = 7.8125 MHz)
Full
Full
Full
II
II
II
30
0.8
35
F
DAC
Cycles
dB
dB
Full
Full
Full
II
II
II
II
II
II
III
II
III
III
10
Bits
MHz
mA
V
%FS
μ
A
LSB
LSB
pF
dBc/Hz
10
2
–0.5
–5.5
0
100
20
+1.5
+5.0
TBD
10
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
±
2
2
0.5
1
5
–100
25
°
C
25
°
C
25
°
C
II
III
III
–60.6
dB
–76.2
dBc
25
°
C
25
°
C
III
III
–77.9
–77
dBc
dBFS
RX PATH CHARACTERISTICS (LFP Bypassed)
Resolution
Conversion Rate
Pipeline Delay, ADC Clock Cycles
Dynamic Performance (A
IN
= –0.5 dBFS, f = 5 MHz)
@ F
OSCIN
= 50 MHz, RX LPF Bypassed
Signal-to-Noise and Distortion Ratio (SINAD)
Effective Number of Bits (ENOB)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
N/A
Full
N/A
N/A
II
N/A
10
Bits
MHz
Cycles
10
50
5.5
Full
Full
Full
Full
Full
III
III
III
III
III
–56.6
9.1
–59.2
–60.1
–66
dB
Bits
dB
dB
dB
RX PATH GAIN/OFFSET
Minimum Programmable Gain
Maximum Programmable Gain
Narrow Band Rx LPF or Rx LPF Bypassed
Wideband Rx LPF
Gain Step Size
Gain Step Accuracy
Gain Range Error
Absolute Gain Error, PGA Gain = 0 dB
25
°
C
I
–6
dB
25
°
C
25
°
C
25
°
C
25
°
C
Full
Full
I
I
I
II
II
II
+36
+30
2
±
0.4
±
1.0
±
0.8
dB
dB
dB
dB
dB
dB
RX PATH INPUT CHARACTERISTICS
Input Voltage Range (Gain = –6 dB)
Input Capacitance
Differential Input Resistance
Input Bandwidth (–3 dB) (Rx LPF Bypassed)
Input Referred Noise (at +36 dB Gain with Filter)
Input Referred Noise (at –6 dB Gain with Filter)
Common-Mode Rejection
Full
25
°
C
25
°
C
25
°
C
25oC
25oC
25oC
III
III
III
III
III
III
III
4
4
270
50
16
684
40
Vppd
pF
MHz
μ
V rms
μ
V rms
dB
(V
S
= 3.3 V 10%, F
OSCIN
= 50 MHz, F
DAC
= 100 MHz, Gain = –6 dB,
R
SET
= 4.02 k
, 100 DAC Load.)
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