參數(shù)資料
型號(hào)： AD9975ABSTEB
廠商： Analog Devices, Inc.
元件分類(lèi)： DC/DC變換器
英文描述： RP10 (E) Series - Powerline Regulated DC-DC Converters; Input Voltage (Vdc): 48V; Output Voltage (Vdc): 5V; 2:1 Wide Input Voltage Range; 10 Watts Output Power; 1.6kVDC Isolation; UL Certified; Fixed Operating Frequency; Six-Sided Continuous Shield; Standard 50.8 x25.4x10.2mm Package; Efficiency to 86%
中文描述： 寬帶調(diào)制解調(diào)器混合信號(hào)前端
文件頁(yè)數(shù)： 15/20頁(yè)
文件大小： 1392K
代理商： AD9975ABSTEB
REV. 0
AD9975
–15–
DIGITAL INTERFACE PORT TIMING
The ADIO[9:0] bus accepts input data-words into the transmit
path when the TXEN pin is high, the RXEN pin is low, and a
clock is present on the TXCLK pin. Figure 3 illustrates the
transmit path input timing.
TXCLK
TXEN
ADIO[9:0]
RXEN
TX0
TX1
TX2
TX3
TX4
t
HD
t
SU
Figure 3. Transmit Data Input Timing Diagram
It should be noted that to clear the transmit path input buffers,
an additional six clock cycles on the TXCLK input are required
after TXEN goes low. The interpolation filters will be “flushed”
with zeros if the clock signal into the TXCLK pin is present for
48 clock cycles after TXEN goes low (the data on the ADIO
bus being irrelevant over this interval).
The output from the receive path will be driven onto the
ADIO[9:0] bus when the RXEN pin is high, and a clock is present
on the RXCLK pin. When both TXEN and RXEN are low, the
ADIO[9:0] bus is three-stated. Figure 4 illustrates the receive
path output timing.
RXCLK
RXEN
ADIO[9:0]
t
VT
RX0
RX1
RX2
RX3
t
HT
Figure 4. Receive Data Output Timing Diagram
SERIAL INTERFACE FOR REGISTER CONTROL
The serial port is a 3-wire serial communications port consisting
of a clock (SCLK), chip select (
SENABLE
), and a bidirectional
data (SDATA) signal. The interface allows read/write access to
all registers that configure the AD9975 internal parameters.
Single or multiple byte transfers are supported as well as MSB
first or LSB first transfer formats.
General Operation of the Serial Interface
Serial communication over the serial interface can be from 1 byte
to 5 bytes in length. The first byte is always the instruction byte.
The instruction byte establishes whether the communication is
going to be a read or write access, the number of data bytes to be
transferred, and the address of the first register to be accessed.
The instruction byte transfer is complete immediately upon the
eighth rising edge of SCLK after
SENABLE
is asserted. Likewise,
the data registers change
immediately
upon writing to the eighth
bit of each data byte.
Instruction Byte
The instruction byte contains the information shown in Table III.
Table III. Instruction Byte Bit Definitions
MSB
LSB
I7
I6
I5
I4
I3
I2
I1
I0
R/W
N1
N0
A4
A3
A2
A1
A0
Bit I7 – R/W
This bit determines whether a read or a write data transfer will
occur after the instruction byte write. Logic high indicates a read
operation, and Logic 0 indicates a write operation.
Bits I6:I5 – N1:N0
These two bits determine the number of bytes to be transferred
during the data transfer cycle. The bit decodes are shown in
Table IV.
Table IV. N1:N0 Bit Map
N1:N0
Description
0:0
0:1
1:0
1:1
Transfer 1 Byte
Transfer 2 Bytes
Transfer 3 Bytes
Transfer 4 Bytes
Bits I4:I0 - A4:A0
These bits determine which register is accessed during the data
transfer portion of the communications cycle. For multibyte
transfers, this address is the starting byte address. The remaining
register addresses are generated by the AD9975.
Serial Interface Port Pin Description
SCLK—Serial Clock
The serial clock pin is used to synchronize data transfers to and
from the AD9975 and to run the internal state machines. SCLK
maximum frequency is 25 MHz. All data transmitted to the
AD9975 is sampled on the rising edge of SCLK. All data read
from the AD9975 is validated on the rising edge of SCLK and is
updated on the falling edge.
SENABLE
—Serial Interface Enable
The
SENABLE
Pin is active low. It enables the serial communi-
cation to the device.
SENABLE
select should stay low during
the entire communication cycle. All input on the serial port is
ignored when
SENABLE
is inactive.
SDATA—Serial Data I/O
The signal on this line is sampled on the first eight rising edges
of SCLK after
SENABLE
goes active. Data is then read from or
written to the AD9975 depending on what was read.
Figures 5 and 6 show the timing relationships between the three
SPI signals.
INSTRUCTION BIT 7
INSTRUCTION BIT 6
t
DS
SENABLE
t
DS
t
SCLK
t
PWL
t
PWH
t
HT
SCLK
SDATA
Figure 5. Timing Diagram Register Write to AD9975
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