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參數(shù)資料
| 型號(hào)： | AD9975ABSTEB |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | DC/DC變換器 |
| 英文描述： | RP10 (E) Series - Powerline Regulated DC-DC Converters; Input Voltage (Vdc): 48V; Output Voltage (Vdc): 5V; 2:1 Wide Input Voltage Range; 10 Watts Output Power; 1.6kVDC Isolation; UL Certified; Fixed Operating Frequency; Six-Sided Continuous Shield; Standard 50.8 x25.4x10.2mm Package; Efficiency to 86% |
| 中文描述： | 寬帶調(diào)制解調(diào)器混合信號(hào)前端 |
| 文件頁(yè)數(shù)： | 12/20頁(yè) |
| 文件大?。?/td> | 1392K |
| 代理商： | AD9975ABSTEB |
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REV. 0
–12–
AD9975
TRANSMIT PATH
The AD9975 transmit path consists of a digital interface port,
a bypassable 2
×
interpolation filter, and a transmit DAC. The
clock signals required by these blocks are generated by the inter-
nal PLL. The block diagram below shows the interconnection
between the major functional components of the transmit path.
INTERPOLATION FILTER
The interpolation filter can be programmed to run at a 2
×
upsampling ratio in either a low-pass filter or band-pass filter
mode. The transfer functions of these two modes are shown in
TPC 1 and TPC 2, respectively. The y-axes of the figures show
the magnitude response of the filters in dB, and the x-axes show
the frequency normalized to F
DAC
. The top trace of the plot shows
the discrete time transfer function of the interpolation filter. The
bottom trace shows the TX path transfer function including the
sin(x)/x transfer function of the DAC. In addition to the two
upsampling modes, the interpolation filter can be programmed
into a pass-through mode if no interpolation filtering is desired.
The table below shows the following parameters as a function of
the mode in which it is programmed.
Latency
– The number of clock cycles from the time a digital
impulse is written to the DAC until the peak value is output at
the TX+ and TX– Pins.
Flush
– The number of clock cycles from the time a digital
impulse is written to the DAC until the output at the TX+ and
TX– Pins settles to zero.
F
PASS
– The frequency band over which the pass-band ripple is
less than the stated magnitude (i.e., 0.1 dB or 1.0 dB).
F
STOP
– The frequency band over which the stop-band attenuation
is greater than the stated magnitude (i.e., 40 dB or 50 dB).
Table I. Interpolation Filters vs. Mode
Register 7[7:4]
0x1
2
×
LPF
30
48
<0.204
<0.207
<0.296
<0.302
0x5
2
×
BPF, Adj. Image
30
48
>0.296, <0.704
>0.293, <0.707
>0.204, <0.796
<0.198, >0.802
Mode
Latency, F
DAC
Clock Cycles
Flush, F
DAC
Clock Cycles
F
PASS
, 0.1 dB
F
PASS
, 1.0 dB
F
STOP
, 40 dB
F
STOP
, 50 dB
DPLL-A CLOCK DISTRIBUTION
Figure 1 shows the clock signals used in the transmit path. The
DAC sampling clock, f
DAC
, is generated by DPLL-A. f
DAC
has a
frequency equal to
L
×
f
OSCIN
, where
L
is the PLL clock multiplier
value and
f
OSCIN
is the frequency of the input to PLL-A. The value
of
L
is programmed through the serial interface port and can be
set to 1, 2, 4, or 8. The transmit path expects a new input sample
at the ADIO interface at a rate of f
DAC
/2 if the interpolation
filter is being used. If the interpolation filter is bypassed, the
transmit path expects a new input sample at the ADIO interface
at a rate of f
DAC.
D/A CONVERTER
The AD9975 DAC provides differential output current on the
TX+ and TX– pins. The values of the output currents are comple-
mentary, meaning they will always sum to I
FS
, the full-scale
current of the DAC. For example, when the current from TX+
is at full scale, the current from TX– is zero. The two currents
will typically drive a resistive load that will convert the output
currents to a voltage. The TX+ and TX– output currents are
inherently ground seeking and should each be connected to
matching resistors, R
L
, that are tied directly to AGND.
The full-scale output current of the DAC is set by the value of
the resistor placed from the FS ADJ pin to AGND. The rela-
tionship between the resistor,
R
SET
, and the full-scale output
current is governed by the following equation:
I
The full-scale current can be set from 2 to 20 mA. Generally, there
is a trade-off between DAC performance and power consumption.
The best DAC performance will be realized at an
I
FS
of 20 mA.
However, the value of
I
FS
adds directly to the overall current
consumption of the device.
The single-ended voltage outputs appearing at the TX+ and
TX– nodes are:
V
V
Note that the full-scale voltage of
V
TX
+
and
V
TX
–
should not
exceed the maximum output compliance range of 1.5 V to pre-
vent signal compression. To maintain optimum distortion and
linearity performance, the maximum voltages at
V
TX
+
and
V
TX
–
should not exceed
±
0.5 V.
The single-ended full-scale voltage at either output node will be:
V
The differential voltage,
V
DIFF
, appearing across V
TX+
and V
TX–
is:
V
and
V
It should be noted that the differential output impedance of the
DAC is 2
×
R
L
and any load connected across the two output
resistors will load down the output voltage accordingly.
R
FS
SET
=
39 4 /
I
I
R
R
TX
TX
L
+
+
=
=
×
×
TX
TX
L
–
–
I
R
FS
FS
L
=
×
I
I
R
DIFF
TX
TX
L
=
×
+
(
–
)
–
I
R
DIFF
FS
FS
L
_
=
×
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