參數(shù)資料
型號(hào)： AD9956
廠商： Analog Devices, Inc.
英文描述： 2.7 GHz DDS-Based AgileRF
中文描述： 2.7千兆赫基于DDS的AgileRF
文件頁數(shù)： 21/32頁
文件大?。?/td> 805K
代理商： AD9956
AD9956
Automatic Synchronization
In automatic synchronization mode, the device is placed into
slave mode and automatically aligns the internal SYNC_CLK to
a master SYNC_CLK signal, supplied on the SYNC_IN input.
When this bit is enabled, the PLL_LOCK is not available as an
output, however, an out-of-lock condition can be detected by
reading Control Function Register 1 and checking the status of
the PLL_LOCK_ERROR bit, CFR1<24>. The automatic
synchronization function is enabled by setting the Control
Function Register 1 automatic synchronization bit, CFR1<3>.
To employ this function at higher clock rates (SYNC_CLK >
62.5 MHz and SYSCLK > 250 MHz), the high speed sync
enable bit (CFR1<0>) should be set as well.
Manual Synchronization, Hardware Controlled
In this mode, the user controls the timing relationship of the
SYNC_CLK with respect to SYSCLK. When hardware manual
synchronization is enabled, the PLL_LOCK/ SYNC_IN pin
becomes a digital input. For each and every rising edge detected
on the SYNC_IN input, the device advances the SYNC_IN
rising edge by one SYSCLK period. When this bit is enabled, the
PLL_LOCK is not available as an output. However, an out-of-
lock condition can be detected by reading Control Function
Register 1 and checking the status of the PLL Lock Error bit,
CFR1<24>. This synchronization function is enabled by setting
the hardware manual synchronization enable bit, CFR1<1>.
Rev. 0 | Page 21 of 32
Manual Synchronization, Software Controlled
In this mode, the user controls the timing relationship between
SYNC_CLK and SYSCLK through software programming.
When the software manual synchronization bit (CFR1<2>) is
set high, the SYNC_CLK is advanced by one SYSCLK cycle.
Once this operation is complete, the bit is cleared. The user can
set this bit repeatedly to advance the SYNC_CLK rising edge
multiple times. Because the operation does not use the
PLL_LOCK/ SYNC_IN pin as a SYNC_IN input, the
PLL_LOCK signal can be monitored on the PLL_LOCK pin
during this operation.
SYSCLK DUT 1
SYNC CLK
DUT1
SYNC CLK DUT2 WITHOUT
SYNC_CLK ALIGNED
SYSCLK DUT 2
SYNCHRONIZATION FUNCTIONS CAN ALIGN DIGITAL CLOCK
RELATIONSHIPS, THEY CANNOT DESKEW THE EDGES OF CLOCKS
SYNC CLK DUT2 WITH
SYNC_CLK ALIGNED
0
1
2
3
0
0
1
2
3
3
0
Figure 28. Synchronization Functions: Capabilities and Limitations
相關(guān)PDF資料
PDF描述
AD9956YCPZ-REEL1 2.7 GHz DDS-Based AgileRF
AD9956YCPZ1 2.7 GHz DDS-Based AgileRF
AD9957 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC
AD9957BSVZ 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC
AD9957BSVZ-REEL 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9956/PCB 制造商:Analog Devices 功能描述:Evaluation Board For AD9956, 2.7 GHz DDS-Based AgileRF Synthesizer 制造商:Analog Devices 功能描述:EVAL BD FOR AD9956, 2.7 GHZ DDS-BASED AGILERF SYNTHESIZER - Trays 制造商:Rochester Electronics LLC 功能描述:400 MSPS 14 BIT DDS EVAL BD. - Bulk
AD9956/PCBZ 功能描述:BOARD EVAL FOR AD9956 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:AgileRF™ 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源
AD9956-VCO/PCB 制造商:Analog Devices 功能描述:EVAL BD FOR AD9956, 2.7 GHZ DDS-BASED AGILERF SYNTHESIZER - Trays 制造商:Analog Devices 功能描述:EVAL CARD ((NS))
AD9956-VCO/PCBZ 功能描述:BOARD EVAL 14BIT 1.8V 48LFCSP RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:AgileRF™ 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源
AD9956XCPZ 制造商:Analog Devices 功能描述:DGTL SYNTHESIZER 48LFCSP EP - Tape and Reel
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